公开(公告)号：US20230328981A1

公开(公告)日：2023-10-12

申请号：US17715662

申请日：2022-04-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki Fujimura ,  Shunsuke Takuma ,  Takashi Kudo ,  Satoshi Shimizu ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

公开(公告)号：US12004347B2

公开(公告)日：2024-06-04

申请号：US17237476

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki Fujimura ,  Satoshi Shimizu ,  Takumi Moriyama

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

公开(公告)号：US20200279861A1

公开(公告)日：2020-09-03

申请号：US16288656

申请日：2019-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya Uryu ,  Satoshi Shimizu ,  Nobuyuki Fujimura

IPC: H01L27/11582 ,  H01L25/065 ,  G11C5/06 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573

Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.