公开(公告)号：US11507498B2

公开(公告)日：2022-11-22

申请号：US16810243

申请日：2020-03-05

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F12/0877 ,  G06F1/24 ,  G06F9/30 ,  G06F9/445 ,  G06F13/16

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US10971199B2

公开(公告)日：2021-04-06

申请号：US16446705

申请日：2019-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Pao-Ling Koh ,  Yuheng Zhang ,  Yan Li

IPC: G11C7/12 ,  H03K19/173 ,  G11C16/26 ,  G11C16/12

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.

公开(公告)号：US10777240B1

公开(公告)日：2020-09-15

申请号：US16453012

申请日：2019-06-26

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Po-Shen Lai ,  Hao Su

IPC: G11C7/22 ,  G11C7/10 ,  G11C13/00 ,  G11C11/16 ,  G11C16/32

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

公开(公告)号：US20200286533A1

公开(公告)日：2020-09-10

申请号：US16453012

申请日：2019-06-26

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Po-Shen Lai ,  Hao Su

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G11C13/00

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

公开(公告)号：US20190018597A1

公开(公告)日：2019-01-17

申请号：US15870390

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Gordon Yee ,  Yibo Yin ,  Tz-Yi Liu

IPC: G06F3/06

Abstract: A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

公开(公告)号：US11087803B2

公开(公告)日：2021-08-10

申请号：US16905229

申请日：2020-06-18

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Po-Shen Lai ,  Hao Su

IPC: G11C7/22 ,  G11C7/10 ,  G11C13/00 ,  G11C11/16 ,  G11C16/32

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.

公开(公告)号：US20210279169A1

公开(公告)日：2021-09-09

申请号：US16906233

申请日：2020-06-19

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F1/24 ,  G06F9/30 ,  G06F12/0877 ,  G06F13/16 ,  G06F9/445

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US20210279168A1

公开(公告)日：2021-09-09

申请号：US16810243

申请日：2020-03-05

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F12/0877 ,  G06F13/16 ,  G06F9/30 ,  G06F9/445 ,  G06F1/24

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US20200321037A1

公开(公告)日：2020-10-08

申请号：US16905229

申请日：2020-06-18

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Po-Shen Lai ,  Hao Su

IPC: G11C7/10 ,  G11C16/32 ,  G11C11/16 ,  G11C7/22 ,  G11C13/00

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.