公开(公告)号：US09098410B2

公开(公告)日：2015-08-04

申请号：US14267814

申请日：2014-05-01

Applicant: Seagate Technology LLC

Inventor： Yan Li ,  Hao Zhong

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  H03M13/29 ,  G06F12/02 ,  H03M13/11

CPC classification number: G06F11/076 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7202 ,  H03M13/1102 ,  H03M13/2957

Abstract: Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used.

Abstract translation: 当对多级单元技术闪存的期望页进行解码时，交叉解码协助解码否则不可校正的错误。 固态盘（SSD）控制器分别在各种页面（例如，上，中，下页）中调整分配给冗余的空间，使得各个页面具有相应的有效误码率（BER），可选地包括交叉解码， 相互接近 或者，控制器调整分配以均衡解码时间（或者可选地，访问时间），可选地包括当存在否则不可校正的错误时由于交叉解码而产生的解码时间（访问时间）。 调整是通过（a）用于ECC冗余的分配和用户数据空间之间的相应比率，和/或（b）各种页面中的每一个的相应编码率和/或编码技术。 或者，控制器通过分配冗余和各种页面的数据来调整分配以最大化总可用容量，假设要使用交叉解码。

公开(公告)号：US10230406B2

公开(公告)日：2019-03-12

申请号：US14594165

申请日：2015-01-11

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Hao Zhong ,  Yan Li ,  Radoslav Danilak ,  Earl T. Cohen

IPC: H03M13/00 ,  H03M13/37 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H03M13/11 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

公开(公告)号：US20160188405A1

公开(公告)日：2016-06-30

申请号：US14945276

申请日：2015-11-18

Applicant: Seagate Technology LLC

Inventor： Yan Li ,  Hao Zhong ,  Radoslav Danilak ,  Earl T Cohen

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C11/56

CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G06F11/1048 ,  G11C11/5628 ,  G11C29/52 ,  H03M13/05 ,  H03M13/2906

Abstract: Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.

Abstract translation: 与闪存一起使用的自适应ECC技术可以改善闪存的使用寿命，可靠性，性能和/或存储容量。 这些技术包括具有各种码率和/或各种码长（提供不同的纠错能力）的ECC方案和错误统计收集/跟踪（例如经由专用的硬件逻辑块）。 所述技术还包括根据ECC方案中的一个或多个的编码/解码，以及至少部分地基于来自错误统计收集/跟踪的信息（例如，经由 硬件逻辑自适应编解码器，从专用误差统计收集/跟踪硬件逻辑块接收输入）。 这些技术还包括随着时间的推移，以各种操作模式（例如，作为MLC页面或SLC页面）选择性地操作闪速存储器的一部分（例如，页面，块）。