SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTERFACING ONE OR MORE STORAGE DEVICES WITH A PLURALITY OF BRIDGE CHIPS

    公开(公告)号:US20170364308A1

    公开(公告)日:2017-12-21

    申请号:US15690396

    申请日:2017-08-30

    CPC classification number: G06F3/0661 G06F3/061 G06F3/0674

    Abstract: Methods, apparatus, and systems, for interfacing one or more storage devices with a plurality of bridge chips. An apparatus may include a memory, a communication bus coupled to a device, and a processor communicatively coupled to the communication bus and the memory. The processor may be configured to implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips. The processor may be further configured to multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.

    TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION

    公开(公告)号:US20170269855A1

    公开(公告)日:2017-09-21

    申请号:US15611062

    申请日:2017-06-01

    Inventor: Radoslav Danilak

    Abstract: The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.

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