公开(公告)号：US20220028812A1

公开(公告)日：2022-01-27

申请号：US17450007

申请日：2021-10-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  H01L21/48

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20180151526A1

公开(公告)日：2018-05-31

申请号：US15871586

申请日：2018-01-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  H01L21/48 ,  B23K3/06

CPC classification number: H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2224/11

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20250062263A1

公开(公告)日：2025-02-20

申请号：US18939985

申请日：2024-11-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  B23K3/06 ,  H01L21/48

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US20180053739A1

公开(公告)日：2018-02-22

申请号：US15240568

申请日：2016-08-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00

CPC classification number: H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/13026

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.