公开(公告)号：US11848346B2

公开(公告)日：2023-12-19

申请号：US17162221

申请日：2021-01-29

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Satoru Wakiyama ,  Kan Shimizu ,  Toshihiko Hayashi ,  Takuya Nakamura ,  Naoki Jyo

IPC: H01L23/00 ,  H01L27/146 ,  H01L23/31

CPC classification number: H01L27/14636 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/81 ,  H01L27/14607 ,  H01L27/14634 ,  H01L27/14643 ,  H01L23/3192 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0239 ,  H01L2224/039 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/03616 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05082 ,  H01L2224/05157 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05547 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2224/81011 ,  H01L2224/8114 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8182 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2224/05157 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01049 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/0346 ,  H01L2924/00014 ,  H01L2224/03616 ,  H01L2924/00014 ,  H01L2224/0361 ,  H01L2924/00012 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81464 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81469 ,  H01L2924/00014 ,  H01L2224/039 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/0361 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.

公开(公告)号：US20190244920A1

公开(公告)日：2019-08-08

申请号：US16384136

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Hsiung Lu ,  Hsuan-Ting Kuo ,  Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/525 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L21/566 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10126 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/04953 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

公开(公告)号：US09997483B2

公开(公告)日：2018-06-12

申请号：US15005461

申请日：2016-01-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Wen-Hsiung Lu ,  Ming-Da Cheng

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/525 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/13 ,  H01L21/566 ,  H01L21/76888 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/02371 ,  H01L2224/0345 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13565 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

公开(公告)号：US20180151526A1

公开(公告)日：2018-05-31

申请号：US15871586

申请日：2018-01-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuhiro SAITO

IPC: H01L23/00 ,  H01L21/48 ,  B23K3/06

CPC classification number: H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/11002 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2224/03 ,  H01L2224/11

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

公开(公告)号：US09960143B2

公开(公告)日：2018-05-01

申请号：US15253878

申请日：2016-09-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Soichi Homma ,  Naoyuki Komuta

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L22/20 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73207 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75901 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81121 ,  H01L2224/8118 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81206 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/81906 ,  H01L2224/81948 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/3656 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state.

公开(公告)号：US20170271285A1

公开(公告)日：2017-09-21

申请号：US15072655

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Kibby B. Horsford ,  Sudeep Mandal

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0332 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/0519 ,  H01L2224/0529 ,  H01L2224/05339 ,  H01L2224/05344 ,  H01L2224/05347 ,  H01L2224/05355 ,  H01L2224/0539 ,  H01L2224/05444 ,  H01L2224/05455 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01005 ,  H01L2924/01015

Abstract: A conductive polymer-solder ball structure is provided. The conductive polymer-solder ball structure includes a wafer having at least one metal pad providing an electrical conductive path to a substrate layer, a conductive polymer pad located directly on the wafer over the at least one metal pad, an electrolessly plated layer located on a surface of the conductive polymer pad, and a solder ball located on a surface of the electrolessly plated layer.

公开(公告)号：US20170186725A1

公开(公告)日：2017-06-29

申请号：US15331957

申请日：2016-10-24

Applicant: Renesas Electronics Corporation

Inventor： Yuichi OTA ,  Kentaro KITA ,  Takehiro OURA ,  Kohei YOSHIDA

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/8238 ,  H01L21/304 ,  H01L23/544 ,  H01L21/683

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/78 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823892 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  H01L2223/5446 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03828 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05644 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11464 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2221/68304

Abstract: A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.

公开(公告)号：US09615464B2

公开(公告)日：2017-04-04

申请号：US14073998

申请日：2013-11-07

Applicant: FUJITSU LIMITED

Inventor： Takashi Kubota ,  Masayuki Kitajima ,  Takatoyo Yamakami ,  Hidehiko Kira

IPC: H05K3/34 ,  B23K35/02 ,  B23K3/08 ,  H01L23/00 ,  H01L31/167 ,  H01S5/022

CPC classification number: H05K3/3484 ,  B23K3/08 ,  B23K35/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L31/167 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27001 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9212 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/181 ,  H01L2924/3841 ,  H01S5/02272 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3494 ,  H05K2203/041 ,  H05K2203/1476 ,  Y10T29/4913 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of mounting a semiconductor element, the method includes: attaching a first solder joint material onto a first pad formed on a substrate supplying a second solder joint material onto the first solder joint material, a second melting point of the second solder joint material being lower than a first melting point of the first solder joint material; arranging the semiconductor element so that a second pad formed on the semiconductor element faces the first pad and a joint gap is provided between the semiconductor element and the substrate; and performing reflow at a reflow temperature lower than the first melting point and higher than the second melting point to join the first solder joint material and the second solder joint material.

公开(公告)号：US20170040273A1

公开(公告)日：2017-02-09

申请号：US15224977

申请日：2016-08-01

Applicant: Qorvo US, Inc.

Inventor： Thomas Scott Morris ,  Robert Hartmann

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5382 ,  H01L24/03 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L2224/03828 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01079 ,  H01L2924/2076

Abstract: The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The disclosed semiconductor package includes a substrate body, a first metal structure having a first finish area and a second finish area, a second metal structure having a third finish area, a surface finish, and a tuning wire. The first metal structure and the second metal structure are formed over the substrate body. The surface finish is provided over the first finish area of the first metal structure and at least a portion of the third finish area of the second metal structure. The surface finish is not provided over the second finish area of the first metal structure. The tuning wire is coupled between the first finish area and at least one portion of the third finish area.

Abstract translation: 本公开涉及一种具有选择性表面光洁度的衬底结构的半导体封装及其制造方法。 所公开的半导体封装包括基板主体，具有第一精加工区域和第二精加工区域的第一金属结构，具有第三精加工区域的第二金属结构，表面光洁度和调谐线。 第一金属结构和第二金属结构形成在衬底本体上。 表面光洁度设置在第一金属结构的第一表面区域和第二金属结构的第三抛光区域的至少一部分上。 在第一金属结构的第二完成区域上没有提供表面光洁度。 调谐线耦合在第一完成区域和第三完成区域的至少一部分之间。

公开(公告)号：US09472522B2

公开(公告)日：2016-10-18

申请号：US14074333

申请日：2013-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/09 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0214 ,  H01L2224/02175 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/0912 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

Abstract translation: 公开了用于半导体器件的封装装置及其制造方法。 在一些实施例中，包装装置包括设置在衬底上的接触垫，以及设置在衬底上的钝化层和接触垫的第一部分，接触垫的第二部分被暴露。 后钝化互连（PPI）线设置在钝化层上并且耦合到接触焊盘的第二部分。 PPI垫设置在钝化层上方并耦合到PPI线。 绝缘材料设置在PPI线上，PPI垫被暴露。 绝缘材料与PPI垫的边缘部分隔开预定距离。