公开(公告)号：US20240211556A1

公开(公告)日：2024-06-27

申请号：US18544191

申请日：2023-12-18

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Seiichi YONEDA ,  Yusuke NEGORO

IPC分类号： G06F21/31 ,  G06F16/22 ,  G06V10/143 ,  G06V40/12 ,  G06V40/13 ,  G06V40/14 ,  H01L25/16 ,  H01L27/146 ,  H01L27/15 ,  H01L29/786 ,  H01L31/12

CPC分类号： G06F21/31 ,  G06F16/22 ,  G06V10/143 ,  G06V40/1318 ,  G06V40/14 ,  H01L25/167 ,  G06V40/1347 ,  G06V40/1365 ,  H01L27/14616 ,  H01L27/15 ,  H01L29/7869 ,  H01L31/12

摘要： A novel authentication system is provided. In addition, a method for recording an unlocking history is provided. The authentication system includes an arithmetic device and an input/output device. The arithmetic device supplies first control data and second control data, and is supplied with a sensor signal. The input/output device includes an electric lock and a reading portion, and the electric lock is unlocked on the basis of the second control data. The reading portion is supplied with the first control data, supplies the sensor signal, and includes a light-emitting element and a pixel array. The light-emitting element emits light including infrared rays, the pixel array includes pixels, the pixels each include an imaging circuit and a photoelectric conversion element, the imaging circuit is electrically connected to the photoelectric conversion element, the imaging circuit includes a transistor, and the transistor includes an oxide semiconductor film.

公开(公告)号：US20240196117A1

公开(公告)日：2024-06-13

申请号：US18584020

申请日：2024-02-22

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Seiichi YONEDA ,  Hiroki INOUE

IPC分类号： H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

CPC分类号： H04N25/78 ,  H04N25/709 ,  H04N25/77 ,  H10K39/32

摘要： An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.

公开(公告)号：US20230133706A1

公开(公告)日：2023-05-04

申请号：US17912560

申请日：2021-04-19

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yusuke NEGORO ,  Seiichi YONEDA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H04N25/40

摘要： An imaging device having an image processing function is provided. The imaging device includes a plurality of pixels. The pixel has a function of generating first data of an n-th frame by supplying a first weight to image data obtained in the n-th frame (n is an integer greater than or equal to 2). The pixel has a function of generating first data of an n−1-th frame by supplying a second weight to image data obtained in the n−1-th frame. The pixel has a function of generating second data by adding the first data of the n−1-th frame and the first data of the n-th frame.

公开(公告)号：US20220416767A1

公开(公告)日：2022-12-29

申请号：US17779675

申请日：2020-11-16

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hiroki INOUE ,  Seiichi YONEDA ,  Yusuke NEGORO

IPC分类号： H03K3/011 ,  H01L27/146 ,  H03K17/56

摘要： A semiconductor device with a small circuit scale is provided. The semiconductor device includes a first circuit and a second circuit. The first circuit includes first to n-th (n is an integer of 2 or more) transistors and the second circuit includes (n+1)-th to 2n-th transistors. The first to n-th transistors are connected in parallel to each other and the (n+1)-th to 2n-th transistors are connected in series to each other. First to n-th signals are supplied to the first circuit and the second circuit. The first circuit has a function of outputting a first potential when each of potentials of the first to n-th signals is lower than or equal to a first reference potential, and outputting a second potential when at least one of the potentials of the first to n-th signals is higher than the first reference potential. The second circuit has a function of outputting a third potential when each of the potentials of the first to n-th signals is higher than a second reference potential, and outputting the first potential when at least one of the potentials of the first to n-th signals is lower than or equal to the second reference potential.

公开(公告)号：US20220415941A1

公开(公告)日：2022-12-29

申请号：US17781152

申请日：2020-12-14

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Seiichi YONEDA ,  Toshiki HAMADA ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC分类号： H01L27/146 ,  H04N5/378 ,  H04N5/3745

摘要： An imaging device with an arithmetic function in which the circuit size is reduced is provided. The imaging device includes a plurality of pixel blocks. Each of the pixel blocks includes N (N is an integer greater than or equal to 1) first circuits, N second circuits, and a third circuit. Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal and has a function of outputting a first signal that is obtained by binarizing the electrical signal to the second circuit. Each of the second circuits has a function of outputting a second signal that is obtained by multiplying the first signal by a weight coefficient to a third circuit. When the N second signals are output to a wiring electrically connected to the third circuit, addition is performed. The first circuit includes a transistor, and an OS transistor is preferably used as the transistor.

公开(公告)号：US20220320172A1

公开(公告)日：2022-10-06

申请号：US17621335

申请日：2020-06-22

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yusuke NEGORO ,  Seiichi YONEDA

IPC分类号： H01L27/146

摘要： The present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. A first stacked body is formed in which a circuit provided with a transistor including a metal oxide in its channel formation region (hereinafter, OS transistor) is stacked over a circuit including a Si transistor. A second stacked body is formed in which an OS transistor is provided over a Si photodiode. Layers including the OS transistors of the first stacked body and the second stacked body are bonded to each other to obtain electrical connection between circuits. With such a structure, even when a structure is employed in which a plurality of circuits having different functions are stacked, the number of polishing steps and bonding steps can be reduced, improving the yield.

公开(公告)号：US20210399726A1

公开(公告)日：2021-12-23

申请号：US17275213

申请日：2019-09-17

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Seiichi YONEDA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

IPC分类号： H03K17/56 ,  H02J50/20

摘要： Provided is a semiconductor device with a novel structure in which the power consumption can be reduced. The semiconductor device includes a sensor, a sample-and-hold circuit to which a sensor signal of the sensor is input, an analog-digital converter circuit to which an output signal of the sample-and-hold circuit is input, a control circuit, a battery, and an antenna. The sample-and-hold circuit includes a first selection circuit, a plurality of signal retention circuits, and a second selection circuit, and the control circuit performs a control so that a potential corresponding to the sensor signal is retained in the plurality of signal retention circuits successively by the first selection circuit in a first period during which power is supplied from the battery, and performs a control so that the output signal based on the potential retained in the plurality of signal retention circuits is output by the second selection circuit in a second period during which power is supplied from outside through the antenna.

公开(公告)号：US20210202549A1

公开(公告)日：2021-07-01

申请号：US17057526

申请日：2019-06-11

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Seiichi YONEDA ,  Hidetomo KOBAYASHI ,  Takashi NAKAGAWA ,  Yusuke NEGORO ,  Shunpei YAMAZAKI

IPC分类号： H01L27/146 ,  H04N5/378 ,  H04N5/353 ,  H04N5/369

摘要： An imaging device that can obtain imaging data corresponding to high-resolution images in a short period of time is provided. The imaging device includes a pixel including a photoelectric conversion element and n (n is an integer more than 2 inclusive) retention circuits. The photoelectric conversion element and the n retention circuits are stacked. One electrode of the photoelectric conversion element is electrically connected to the first to n-th retention circuits. The retention circuits include OS transistors with an extremely low off-state current feature, and can retain imaging data for a long time. In the first to n-th periods, the imaging device obtains the first to n-th imaging data and retains it in the first to n-th retention circuits. Then, the first to n-th imaging data retained in the first to n-th retention circuits are read out. The read imaging data is output outside the imaging data through AD conversion.

公开(公告)号：US20200020298A1

公开(公告)日：2020-01-16

申请号：US16469260

申请日：2017-12-11

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yuki OKAMOTO ,  Seiichi YONEDA

IPC分类号： G09G5/00 ,  G09G3/3275 ,  G09G3/3266

摘要： Image processing in accordance with the shape of a display device is performed at high speed with low power consumption, without the use of a large frame memory or a high-throughput GPU. Used is a data conversion circuit including: a latch circuit that takes in data from input data in synchronization with a writing clock signal and stores the data as writing data; a memory circuit that stores the writing data and outputs the writing data to an external circuit as readout data in synchronization with a readout clock signal; and a clock selection control circuit. The writing clock signal is one of a plurality of clock signals with different frequencies and is output in accordance with control by the clock selection control circuit.

公开(公告)号：US20160293655A1

公开(公告)日：2016-10-06

申请号：US15083755

申请日：2016-03-29

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Seiichi YONEDA ,  Takuro OHMARU ,  Yuki OKAMOTO

IPC分类号： H01L27/146 ,  H01L31/0272 ,  H01L29/786

CPC分类号： H01L27/14643 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14665 ,  H01L29/7869 ,  H01L31/02005 ,  H01L31/022408 ,  H01L31/0272 ,  H01L31/107

摘要： To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

摘要翻译： 提供能够进行高速读取的成像装置。 成像装置包括光电二极管，第一晶体管，第二晶体管，第三晶体管和第四晶体管。 第一晶体管的背栅电极电连接到可以提供高于第一晶体管的源极电位的电位和低于第一晶体管的源极电位的电位的布线。 第二晶体管的背栅极电连接到可以提供高于第二晶体管的源极电位的电位的布线。 第三晶体管的背栅电极电连接到可以提供高于第三晶体管的源极电位的电位和低于第三晶体管的源极电位的电位的布线。