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公开(公告)号：US20160314851A1
公开(公告)日：2016-10-27
申请号：US15203885
申请日：2016-07-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko AMANO , Kouhei TOYOTAKA , Hiroyuki MIYAKE , Aya MIYAZAKI , Hideaki SHISHIDO , Koji KUSUNOKI
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G09G2300/0809 , G09G2310/0286 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H01L2924/0002 , H03K19/0013 , H05K7/02 , H01L2924/00
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US20160042807A1
公开(公告)日：2016-02-11
申请号：US14921073
申请日：2015-10-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroyuki MIYAKE , Seiko AMANO
IPC: G11C19/28
CPC classification number: G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2300/0417 , G09G2310/0267 , G09G2320/0223 , G09G2320/0285
Abstract: The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.
Abstract translation: 移位寄存器包括第一至第四触发器。 在第一时间段中处于第一电压状态并且在第二至第四周期中处于第二电压状态的第一时钟信号被输入到第一触发器。 第二时钟信号在第二周期和第四周期中的第二周期和第二电压状态下处于第一电压状态，并被输入到第二触发器。 第三时钟信号在第一，第二和第四周期处于第二电压状态，并且在第三周期中处于第一电压状态，被输入到第三触发器。 第四时钟信号在第一和第二周期处于第二电压状态，并且在第四周期中处于第一电压状态，被输入到第四触发器。
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公开(公告)号：US20150364211A1
公开(公告)日：2015-12-17
申请号：US14831939
申请日：2015-08-21
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko AMANO , Hiroyuki MIYAKE
CPC classification number: G09G3/3677 , G06F1/3265 , G06F3/038 , G09G3/3266 , G09G5/008 , G09G2300/0809 , G09G2300/0871 , G09G2310/0205 , G09G2310/0248 , G09G2310/0286 , G09G2310/08 , G09G2320/0247 , G09G2330/021 , G11C19/28 , H01L27/124
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
Abstract translation: 在移位寄存器的脉冲输出电路中，连接到与下一级的脉冲输出电路连接的输出部中的晶体管的电源线被设定为低电位驱动电压，电源线 连接到连接到扫描信号线的输出部分中的晶体管被设置为可变电位驱动电压。 可变电位驱动电压是正常模式下的低电位驱动电压，可以是高电位驱动电压或分批模式的低电位驱动电压。 在批量模式中，可以在批次中以相同的定时将显示扫描信号输出到多条扫描信号线。
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公开(公告)号：US20190392914A1
公开(公告)日：2019-12-26
申请号：US16458304
申请日：2019-07-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko AMANO , Kouhei TOYOTAKA , Hiroyuki MIYAKE , Aya MIYAZAKI , Hideaki SHISHIDO , Koji KUSUNOKI
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US20160268365A1
公开(公告)日：2016-09-15
申请号：US15162667
申请日：2016-05-24
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko AMANO
CPC classification number: H01L27/3276 , H01L27/1214 , H01L27/1244 , H01L27/3262 , H01L51/5246 , H01L51/5253 , H01L2251/5338 , H05B33/04
Abstract: It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.
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Patent Agency Ranking
公开(公告)号：US20140306228A1
公开(公告)日：2014-10-16
申请号：US14256660
申请日：2014-04-18
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko AMANO
IPC: H01L27/12
CPC classification number: H01L27/3276 , H01L27/1214 , H01L27/1244 , H01L27/3262 , H01L51/5246 , H01L51/5253 , H01L2251/5338 , H05B33/04
Abstract: It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.
Abstract translation: 本发明的目的是防止绝缘膜在绝缘膜与密封区域相邻的部分中剥离。 在第一基板104上设置有设置有发光元件的像素部分100，源极驱动器101，栅极驱动器102和密封区域103。 发光元件通过密封剂108密封在第一基板104和第二基板110之间。绝缘膜107用作发光元件的分隔壁。 与密封区域103相邻的绝缘膜107的端部与由用作布线的导电膜106的侧面和上表面形成的台阶不重叠。
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公开(公告)号：US20240212774A1
公开(公告)日：2024-06-27
申请号：US18596906
申请日：2024-03-06
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko AMANO , Kouhei TOYOTAKA , Hiroyuki MIYAKE , Aya MIYAZAKI , Hideaki SHISHIDO , Koji KUSUNOKI
CPC classification number: G11C19/28 , G09G3/3677 , G09G3/3696 , G11C19/184 , H01L25/03 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/127 , H01L27/1288 , H03K19/0013 , H05K7/02 , G09G2300/0809 , G09G2310/0286 , H01L2924/0002
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US20220284976A1
公开(公告)日：2022-09-08
申请号：US17749309
申请日：2022-05-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko AMANO , Kouhei TOYOTAKA , Hiroyuki MIYAKE , Aya MIYAZAKI , Hideaki SHISHIDO , Koji KUSUNOKI
Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L, of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
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公开(公告)号：US20210390921A1
公开(公告)日：2021-12-16
申请号：US17458656
申请日：2021-08-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Seiko AMANO , Hiroyuki MIYAKE
IPC: G09G3/36 , G06F3/038 , G09G3/3266 , G11C19/28 , G06F1/3234 , H01L27/12
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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公开(公告)号：US20240347018A1
公开(公告)日：2024-10-17
申请号：US18613713
申请日：2024-03-22
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiko AMANO , Hiroyuki MIYAKE
IPC: G09G3/36 , G06F1/3234 , G06F3/038 , G09G3/3266 , G09G5/00 , G11C19/28 , H01L27/12
CPC classification number: G09G3/3677 , G06F1/3265 , G06F3/038 , G09G3/3266 , G11C19/28 , H01L27/124 , G09G5/008 , G09G2300/0809 , G09G2300/0871 , G09G2310/0205 , G09G2310/0248 , G09G2310/0286 , G09G2310/08 , G09G2320/0247 , G09G2330/021
Abstract: In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
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