公开(公告)号：US09373540B2

公开(公告)日：2016-06-21

申请号：US14465541

申请日：2014-08-21

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun

IPC: H01L21/768 ,  H01L27/115 ,  H01L23/50

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes conductive patterns and interlayer insulating patterns having a stair structure and being alternately stacked, pad patterns connected to end portions of upper surfaces of the conductive patterns exposed through the stair structure, and a channel film penetrating the conductive patterns and the interlayer insulating patterns.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括导电图案和层间绝缘图案，其具有阶梯结构并交替堆叠，焊接图案连接到通过楼梯结构暴露的导电图案的上表面的端部，以及通过导电图案和层间绝缘的沟道膜 模式。

公开(公告)号：US09911751B2

公开(公告)日：2018-03-06

申请号：US15155937

申请日：2016-05-16

Applicant: SK hynix Inc.

Inventor： Woo June Kwon ,  Jong Hoon Kim ,  Chan Sun Hyun

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11565 ,  H01L27/11568 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

公开(公告)号：US09484247B2

公开(公告)日：2016-11-01

申请号：US15092678

申请日：2016-04-07

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.

Abstract translation: 半导体器件包括交替堆叠的导电层和绝缘层的堆叠结构; 配置成穿过堆叠结构的半导体图案; 以及分别电耦合到所述导电层的接触插塞，其中每个所述导电层包括具有第一厚度的第一区域和电耦合到所述第一区域的第二区域和大于所述第一厚度的第二厚度，以及 位于上部导电层的第二区域下方的下部导电层的第二区域。

公开(公告)号：US09368511B2

公开(公告)日：2016-06-14

申请号：US14951018

申请日：2015-11-24

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun ,  Myung Kyu Ahn ,  Woo June Kwon

IPC: H01L27/115 ,  H01L27/06 ,  H01L27/24 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L27/11582 ,  G11C2213/71 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

公开(公告)号：US09754962B2

公开(公告)日：2017-09-05

申请号：US15152167

申请日：2016-05-11

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun ,  Myung Kyu Ahn ,  Woo June Kwon

IPC: H01L27/115 ,  H01L27/06 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/24 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  G11C2213/71 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

公开(公告)号：US09224751B2

公开(公告)日：2015-12-29

申请号：US14453403

申请日：2014-08-06

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun ,  Myung Kyu Ahn ,  Woo June Kwon

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  G11C2213/71 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/2481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract translation: 半导体器件包括彼此层叠并间隔开的层间电介质，穿过层间电介质的沟道层，各自围绕要设置在层间电介质之间的沟道层的侧壁的线图案区域，沿着 线路图案区域和沟道层的侧壁中的每一个，沿着每个线图案区域的第一区域的表面形成在阻挡图案上的反应防止图案，第一区域与沟道层相邻，保护 填充在反应防止图案的第一区域中的图案，以及填充在每个线图案区域的第二区域中的第一金属层。

公开(公告)号：US10141332B2

公开(公告)日：2018-11-27

申请号：US15876592

申请日：2018-01-22

Applicant: SK hynix Inc.

Inventor： Woo June Kwon ,  Jong Hoon Kim ,  Chan Sun Hyun

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/311 ,  H01L23/544

Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.

公开(公告)号：US09589980B2

公开(公告)日：2017-03-07

申请号：US14258720

申请日：2014-04-22

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun ,  Wan Soo Kim ,  Myung Kyu Ahn ,  Young Bin Ko

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/2472 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L45/04

Abstract: A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled.

Abstract translation: 半导体器件包括在其侧壁上形成有突起的第一半导体图案，以及分别耦合到第一半导体图案并且在远离第一半导体图案和第二半导体图案耦合的接合表面的宽度上增加的第二半导体图案。

公开(公告)号：US09337091B2

公开(公告)日：2016-05-10

申请号：US14601709

申请日：2015-01-21

Applicant: SK hynix Inc.

Inventor： Chan Sun Hyun

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer.