公开(公告)号：US12027209B2

公开(公告)日：2024-07-02

申请号：US17688173

申请日：2022-03-07

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Chi Wook An ,  Un Sang Lee

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483

摘要： A memory device comprises a plurality of memory cells each having a threshold voltage corresponding to any one of a plurality of program states according to target data to be stored by performing a program operation, page buffers configured to store data provided from a memory controller, a data conversion controller configured to control the page buffers to convert the data into the target data including a plurality of logical page bits and a program operation controller configured to perform the program operation to store the target data in the plurality of memory cells, wherein the plurality of logical page bits include at least one logical page bit distinguishing even program states from odd program states among the plurality of program states and remaining logical page bits other than the at least one logical page bit having a same value as at least one program state among adjacent program states.

公开(公告)号：US11600322B2

公开(公告)日：2023-03-07

申请号：US17227907

申请日：2021-04-12

申请人： SK hynix Inc.

发明人： Byoung Young Kim ,  Jong Woo Kim ,  Young Cheol Shin

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

摘要： A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.

公开(公告)号：US11195586B2

公开(公告)日：2021-12-07

申请号：US16881852

申请日：2020-05-22

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Chi Wook An ,  Un Sang Lee ,  Hwang Huh

IPC分类号： G11C7/00 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10 ,  G11C16/04

摘要： A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including memory cells that are programmed into a plurality of program states, a peripheral circuit configured to perform a read operation on the memory cell array, and control logic configured to control the peripheral circuit to perform the read operation and to control the peripheral circuit to perform a masking process on first memory cells having a threshold voltage level higher than a first read level and second memory cells having a threshold voltage level lower than a second read level among the memory cells during the read operation.

公开(公告)号：US12062403B2

公开(公告)日：2024-08-13

申请号：US17487705

申请日：2021-09-28

申请人： SK hynix Inc.

发明人： Soo Yeol Chai ,  Jong Woo Kim

IPC分类号： G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C7/1039 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

摘要： A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

公开(公告)号：US11961561B2

公开(公告)日：2024-04-16

申请号：US17557342

申请日：2021-12-21

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Young Cheol Shin

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

摘要： The present technology relates to an electronic device. According to the present technology, a memory device having improved verify accuracy may include a memory block including memory cells, a read and write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verify operation of comparing sensing voltages with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verify operation. The control logic controls performing a first verify operation on each of page buffer groups having a same logical group number, and performing a second verify operation on each of page buffer groups having a same physical group number, and the current sensing circuit outputs a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.

公开(公告)号：US11908532B2

公开(公告)日：2024-02-20

申请号：US17580274

申请日：2022-01-20

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Young Cheol Shin

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10

摘要： Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation for storing data in selected memory cells among the plurality of memory cells, and a control logic circuit configured to control the peripheral circuit to form threshold voltage distributions corresponding to target program states corresponding to the data to be stored in the selected memory cells, respectively, wherein the control logic controls the peripheral circuit to perform a main verify operation for any one of the target program states of the selected memory cells when a pre-verify operation for the any one of the target program states has passed.

公开(公告)号：US11282583B2

公开(公告)日：2022-03-22

申请号：US16940887

申请日：2020-07-28

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Yu Jong Noh

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

摘要： A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit is configured to perform a program operation on the memory cell array. The control logic is configured to control the program operation performed by the peripheral circuit. Each of the plurality of memory blocks is coupled to a drain select line, a plurality of word lines, and first and second source select lines that correspond to the memory block. During a program operation performed on a first memory block selected as a program target, among the plurality of memory blocks, the control logic controls the peripheral circuit so that a first source select line of a second memory block that is not selected as the program target, among the plurality of memory blocks, floats.

公开(公告)号：US11495305B2

公开(公告)日：2022-11-08

申请号：US17003402

申请日：2020-08-26

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Young Cheol Shin

IPC分类号： G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/04

摘要： A semiconductor memory device includes a memory cell array and a peripheral circuit. The memory cell array includes at least two planes. The peripheral circuit performs a memory operation on a selected plane of the at least two planes during a single plane operation and performs a dummy operation on an unselected plane of the at least two planes.

公开(公告)号：US12125543B2

公开(公告)日：2024-10-22

申请号：US18073276

申请日：2022-12-01

申请人： SK hynix Inc.

发明人： Eun Woo Jo ,  Jong Woo Kim

IPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483

摘要： A semiconductor memory device includes a memory cell array including memory cells, a peripheral circuit performing a read/verify operation of selected memory cells, and a control logic circuit controlling the read/verify operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to a selected word line connected to the selected memory cells, float unselected word lines adjacent to the selected word line among unselected word lines, apply a first under-drive voltage lower than the first voltage to the selected word line during at least a partial period in which the unselected word lines adjacent to the selected word line are floated, and apply a second voltage higher than the first under-drive voltage and lower than the first voltage to the selected word line.

公开(公告)号：US11887673B2

公开(公告)日：2024-01-30

申请号：US17575274

申请日：2022-01-13

申请人： SK hynix Inc.

发明人： Jong Woo Kim ,  Young Cheol Shin

IPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/14 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/3459

摘要： The present technology relates to an electronic device. A memory device according to the present technology includes a plurality of memory cells connected to a word line, an operation controller configured to apply a first or a second read voltage to the word line and to obtain data that is stored in the plurality of memory cells through bit lines that are respectively connected to the plurality of memory cells, and a read voltage controller configured to control the operation controller to read the data that is stored in the plurality of memory cells by using the second read voltage, and to read the data that is stored in the plurality of memory cells by using the first read voltage according to the number of off cells that are counted based on the data that is read by using the second read voltage, in response to a read command.