公开(公告)号：US20180366190A1

公开(公告)日：2018-12-20

申请号：US16114072

申请日：2018-08-27

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C13/00 ,  G11C16/26 ,  G11C7/02 ,  G11C11/16 ,  G11C8/08 ,  G11C7/10

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

公开(公告)号：US20170236568A1

公开(公告)日：2017-08-17

申请号：US15291945

申请日：2016-10-12

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C7/10 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C13/0064 ,  G11C7/02 ,  G11C7/1072 ,  G11C8/08 ,  G11C11/161 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/26

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

公开(公告)号：US10062436B2

公开(公告)日：2018-08-28

申请号：US15291945

申请日：2016-10-12

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/16 ,  G11C16/26 ,  G11C7/02 ,  G11C8/08

CPC classification number: G11C13/0064 ,  G11C7/02 ,  G11C7/08 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/08 ,  G11C11/161 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/26

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

公开(公告)号：US20180158523A1

公开(公告)日：2018-06-07

申请号：US15704995

申请日：2017-09-14

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/002

Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.

公开(公告)号：US10121537B2

公开(公告)日：2018-11-06

申请号：US15704995

申请日：2017-09-14

Applicant: SK hynix Inc.

Inventor： Kwang-Myoung Rho

IPC: G11C7/10 ,  G11C11/16 ,  G11C13/00

Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.