公开(公告)号：US11764217B2

公开(公告)日：2023-09-19

申请号：US17744141

申请日：2022-05-13

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US11362088B2

公开(公告)日：2022-06-14

申请号：US17039051

申请日：2020-09-30

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US09941263B2

公开(公告)日：2018-04-10

申请号：US15052521

申请日：2016-02-24

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

公开(公告)号：US12094878B2

公开(公告)日：2024-09-17

申请号：US18450146

申请日：2023-08-15

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US11114437B2

公开(公告)日：2021-09-07

申请号：US16842599

申请日：2020-04-07

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66

Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

公开(公告)号：US10833075B2

公开(公告)日：2020-11-10

申请号：US16211919

申请日：2018-12-06

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

公开(公告)号：US10304825B2

公开(公告)日：2019-05-28

申请号：US15990042

申请日：2018-05-25

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/088 ,  H03K19/00 ,  H01L21/8234 ,  H01L29/66

Abstract: A standard cell having a NOR function. The cell including first and second p-channel transistors connected in series between an output node and a power supply node, and first and second n-channel transistors connected in parallel between the output node and a ground node. The first p-channel transistor includes n fin transistor(s), the n fin transistor(s) having a same gate length and a same gate width, the first p-channel transistor having its gate connected to a first input node, and the second p-channel transistor includes m fin transistors, the m fin transistors having the same gate length and the same gate width as the n fin transistor(s), the second p-channel transistor having its gate connected to a second input node, the first n-channel transistor having its gate connected to the first input node, and the second n-channel transistor having its gate connected to the second input node.

公开(公告)号：US12080805B2

公开(公告)日：2024-09-03

申请号：US18358689

申请日：2023-07-25

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/00 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/06 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/0207 ,  H01L2027/11874 ,  H01L27/1203

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire PET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US11764224B2

公开(公告)日：2023-09-19

申请号：US17887913

申请日：2022-08-15

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/00 ,  H01L27/118 ,  H01L29/06 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/06 ,  H01L21/823871 ,  H01L2027/11812 ,  H01L2027/11861 ,  H01L2027/11864 ,  H01L2027/11866

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

公开(公告)号：US11688814B2

公开(公告)日：2023-06-27

申请号：US17674568

申请日：2022-02-17

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/775

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.