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公开(公告)号：US10541694B2
公开(公告)日：2020-01-21
申请号：US16238092
申请日：2019-01-02
Applicant: SOCIONEXT INC.
Inventor： Hajime Sato , Kenta Aruga
Abstract: A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.
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公开(公告)号：US20180205388A1
公开(公告)日：2018-07-19
申请号：US15921337
申请日：2018-03-14
Applicant: Socionext Inc.
Inventor： Kenta Aruga , Yasuhiro Mizuno , Masato Yoshioka
IPC: H03M1/06
CPC classification number: H03M1/0678 , H03M1/069 , H03M1/38 , H03M1/46 , H03M1/462 , H03M1/68 , H03M1/765 , H03M1/804 , H04N5/4401 , H04N5/50
Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.
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公开(公告)号：US10164651B2
公开(公告)日：2018-12-25
申请号：US15921337
申请日：2018-03-14
Applicant: SOCIONEXT INC.
Inventor： Kenta Aruga , Yasuhiro Mizuno , Masato Yoshioka
Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.
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公开(公告)号：US12081251B2
公开(公告)日：2024-09-03
申请号：US18057054
申请日：2022-11-18
Applicant: Socionext Inc.
Inventor： Kenta Aruga , Takashi Miyazaki , Daisuke Kimura , Yasuhiro Majima , Shunichiro Masaki , Shunsuke Hirano
CPC classification number: H04B1/10 , H04L27/0008
Abstract: A processing circuit includes: a clock generating circuit configured to generate, based on a reference clock signal and a frequency division ratio, a first clock signal; a frequency dividing and delay circuit configured to generate a second clock signal to have a first phase difference with the reference clock signal by dividing the frequency of the first clock signal and delaying the first clock signal based on a phase shift set signal and the frequency division ratio; an analog-to-digital converter circuit configured to convert an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; and a control circuit configured to generate the conversion trigger signal to have the same cycle as the second clock signal based on the frequency division ratio and the first clock signal.
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