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公开(公告)号：US09728458B2
公开(公告)日：2017-08-08
申请号：US14416895
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
IPC: H01L21/00 , H01L21/78 , H01L21/268 , H01L21/304 , H01L21/683 , H01L33/00
CPC classification number: H01L21/78 , H01L21/268 , H01L21/304 , H01L21/6835 , H01L21/7813 , H01L33/0079
Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
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公开(公告)号：US11088016B2
公开(公告)日：2021-08-10
申请号：US16685938
申请日：2019-11-15
Applicant: Soitec
Inventor： Marcel Broekaart , Ionut Radu , Chrystelle Lagahe Blanchard
IPC: H01L21/762 , H01L27/146 , H01L23/544
Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
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3.发明授权Methods of forming semiconductor structures including MEMS devices and integrated circuits on common sides of substrates, and related structures and devices 有权在基板的共同侧上形成包括MEMS器件和集成电路的半导体结构以及相关结构和器件的方法公开(公告)号：US09511996B2
公开(公告)日：2016-12-06
申请号：US14416860
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
CPC classification number: B81C1/00246 , B81B7/0006 , B81B2201/0271 , B81B2207/015 , B81C1/00238 , B81C2203/0735 , B81C2203/0792 , H03H9/10
Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
Abstract translation: 方法用于形成半导体器件，其包括集成电路和与集成电路可操作地耦合的微机电系统（MEMS）器件。 可以在衬底的表面上制造集成电路的至少一部分，并且可以在集成电路的至少一部分上形成MEMS器件。 MEMS器件可以与集成电路可操作地耦合。 使用这种方法形成包括这种结构的半导体结构和电子器件。
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4.发明授权Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices 有权在衬底的相对侧上形成包括MEMS器件和集成电路的半导体结构以及相关结构和器件的方法公开(公告)号：US09481566B2
公开(公告)日：2016-11-01
申请号：US14416825
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
CPC classification number: B81B7/007 , B81B2201/0271 , B81B2207/012 , B81B2207/015 , B81C1/00238 , B81C1/00246 , B81C1/00301 , B81C2203/0735 , B81C2203/0792 , H01L2224/16 , H03H9/10
Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
Abstract translation: 形成包括集成电路的半导体器件和与集成电路可操作耦合的微机电系统（MEMS）器件的方法包括形成导电通孔，该导电通孔至少部分地穿过衬底，从衬底的第一主表面向相对的第二主表面延伸 的衬底，以及在衬底的第一主表面上制造集成电路的至少一部分。 MEMS器件设置在衬底的第二主表面上，并且MEMS器件使用至少一个导电通孔与集成电路操作耦合。 使用这种方法制造结构和装置。
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Patent Agency Ranking
公开(公告)号：US20200161172A1
公开(公告)日：2020-05-21
申请号：US16685938
申请日：2019-11-15
Applicant: Soitec
Inventor： Marcel Broekaart , Ionut Radu , Chrystelle Lagahe Blanchard
IPC: H01L21/762 , H01L27/146 , H01L23/544
Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
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6.发明申请METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON COMMON SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES 有权形成半导体结构的方法，其中包括MEMS器件和基片通用面的集成电路，以及相关的结构和器件公开(公告)号：US20150210540A1
公开(公告)日：2015-07-30
申请号：US14416860
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
CPC classification number: B81C1/00246 , B81B7/0006 , B81B2201/0271 , B81B2207/015 , B81C1/00238 , B81C2203/0735 , B81C2203/0792 , H03H9/10
Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
Abstract translation: 方法用于形成半导体器件，其包括集成电路和与集成电路可操作地耦合的微机电系统（MEMS）器件。 可以在衬底的表面上制造集成电路的至少一部分，并且可以在集成电路的至少一部分上形成MEMS器件。 MEMS器件可以与集成电路可操作地耦合。 使用这种方法形成包括这种结构的半导体结构和电子器件。
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7.发明申请METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MEMS DEVICES AND INTEGRATED CIRCUITS ON OPPOSING SIDES OF SUBSTRATES, AND RELATED STRUCTURES AND DEVICES 有权形成包括MEMS器件的半导体结构的方法和基板对准面的集成电路及其相关结构和器件公开(公告)号：US20150191344A1
公开(公告)日：2015-07-09
申请号：US14416825
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
CPC classification number: B81B7/007 , B81B2201/0271 , B81B2207/012 , B81B2207/015 , B81C1/00238 , B81C1/00246 , B81C1/00301 , B81C2203/0735 , B81C2203/0792 , H01L2224/16 , H03H9/10
Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
Abstract translation: 形成包括集成电路的半导体器件和与集成电路可操作耦合的微机电系统（MEMS）器件的方法包括形成导电通孔，该导电通孔至少部分地穿过衬底，从衬底的第一主表面向相对的第二主表面延伸 的衬底，以及在衬底的第一主表面上制造集成电路的至少一部分。 MEMS器件设置在衬底的第二主表面上，并且MEMS器件使用至少一个导电通孔与集成电路操作耦合。 使用这种方法制造结构和装置。
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公开(公告)号：US20160197006A1
公开(公告)日：2016-07-07
申请号：US14903961
申请日：2014-06-24
Applicant: SOITEC
Inventor： Marcel Broekaart , Ionut Radu , Chrystelle Lagahe Blanchard
IPC: H01L21/762 , H01L23/544
CPC classification number: H01L21/76254 , H01L23/544 , H01L27/14687 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
Abstract: The disclosure relates to a process for locating devices, the process comprising the following steps: a) providing a carrier substrate comprising: a device layer; and alignment marks; b) providing a donor substrate; c) forming a weak zone in the donor substrate, the weak zone delimiting a useful layer; d) assembling the donor substrate and the carrier substrate; and e) fracturing the donor substrate in the weak zone so as to transfer the useful layer to the device layer; wherein the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
Abstract translation: 本公开涉及一种用于定位设备的方法，该方法包括以下步骤：a）提供载体衬底，其包括：器件层; 和对准标记; b）提供供体底物; c）在施主衬底中形成弱区，限定有用层的弱区; d）组装供体衬底和载体衬底; 以及e）在所述弱区中破坏所述施主衬底，以将所述有用层转移到所述器件层; 其中对准标记被放置在形成在器件层中的空腔中，空腔具有与器件层的自由表面齐平的孔。
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9.发明申请METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES USING LASER LIFT-OFF PROCESS, AND RELATED SEMICONDUCTOR STRUCTURES 有权使用激光提升过程制造半导体结构的方法和相关半导体结构公开(公告)号：US20150179520A1
公开(公告)日：2015-06-25
申请号：US14416895
申请日：2013-07-08
Applicant: Soitec
Inventor： Mariam Sadaka , Bernard Aspar , Chrystelle Lagahe Blanchard
IPC: H01L21/78 , H01L21/304 , H01L21/683 , H01L21/268
CPC classification number: H01L21/78 , H01L21/268 , H01L21/304 , H01L21/6835 , H01L21/7813 , H01L33/0079
Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
Abstract translation: 制造半导体结构的方法包括将载体晶片结合在衬底上，去除衬底的至少一部分，通过载体晶片传输激光辐射并削弱衬底和载体晶片之间的结合，并将载体晶片与 基质。 其他方法包括在衬底上形成电路，在衬底中形成沟槽以限定非引线半导体管芯，将载体衬底接合在非引线半导体管芯上方，将激光辐射传输通过载体衬底并削弱未加掩模的半导体管芯与载体衬底之间的接合 并且将载体衬底与未折叠的半导体管芯分离。 一些方法包括使衬底的至少一部分变薄，使得多个未折叠的半导体管芯接合到载体衬底。
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