公开(公告)号：US12143093B2

公开(公告)日：2024-11-12

申请号：US18352972

申请日：2023-07-14

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  A61B5/00 ,  A61B5/145 ,  A61B5/1459 ,  H03H3/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H10N30/072 ,  H10N30/085 ,  H10N30/87 ,  H10N39/00

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US11742233B2

公开(公告)日：2023-08-29

申请号：US17135340

申请日：2020-12-28

Applicant: Soitec

Inventor： Marcel Broekaart ,  Ionut Radu ,  Didier Landru

IPC: H01L21/683 ,  H01L21/48 ,  H01L21/762

CPC classification number: H01L21/6835 ,  H01L21/4803 ,  H01L21/76251 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68381

Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.

公开(公告)号：US20230230874A1

公开(公告)日：2023-07-20

申请号：US18007145

申请日：2021-06-23

Applicant: Soitec

Inventor： Bruno Clemenceau ,  Ludovic Ecarnot ,  Aymen Ghorbel ,  Marcel Broekaart ,  Daniel Delprat ,  Séverin Rouchier ,  Stephane Thieffry ,  Carine Duret

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/6835 ,  H01L21/02274

Abstract: A method for transferring a thin layer onto a carrier substrate comprises preparing a carrier substrate using a preparation method involving supplying a base substrate having, on a main face, a charge-trapping layer and forming a dielectric layer having a thickness greater than 200 nm on the charge-trapping layer. Once the dielectric layer is formed, the ionized deposition and sputtering of the dielectric layer are simultaneously performed. The transfer method also comprises assembling, by way of molecular adhesion and with an unpolished free face of the dielectric layer, a donor substrate to the dielectric layer of the carrier substrate, the donor substrate having an embrittlement plane defining the thin layer. Finally, the method comprises splitting the donor substrate at the embrittlement plane to release the thin layer and to transfer it onto the carrier substrate.

公开(公告)号：US20210407849A1

公开(公告)日：2021-12-30

申请号：US17414858

申请日：2020-01-08

Applicant: Soitec

Inventor： Marcel Broekaart ,  Damien Parissi

IPC: H01L21/762 ,  H01L21/02

Abstract: A process for producing a receiver substrate for a semiconductor-on-insulator structure for radiofrequency application comprises the following steps: providing a semiconductor substrate comprising a base substrate made of monocrystalline material and a charge-trapping layer made of polycrystalline silicon arranged on the base substrate; oxidizing the charge-trapping layer to form an oxide layer arranged on the charge-trapping layer. The oxidation of the charge-trapping layer is performed at least partly at a temperature lower than or equal to 875° C., in the following manner: starting the oxidization at a first temperature (T1) between 750° C. and 1000° C.; decreasing the temperature down to a second temperature (T2), lower than the first temperature (T1), between 750° C. and 875° C.; continuing the oxidization at the second temperature (T2).

公开(公告)号：US20200228088A1

公开(公告)日：2020-07-16

申请号：US16829604

申请日：2020-03-25

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H01L41/312 ,  H03H3/02 ,  H01L27/20 ,  H01L41/047 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US20160141198A1

公开(公告)日：2016-05-19

申请号：US14938492

申请日：2015-11-11

Applicant: Soitec

Inventor： Marcel Broekaart

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L21/02002 ,  H01L21/185 ,  H01L21/7806 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363

Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.

Abstract translation: 本发明涉及一种使用临时衬底将活性层转移到最终衬底的方法，所述活性层包括具有三维表面拓扑结构的第一侧，所述方法包括：将活性物质的第一面接合的第一步骤 层到临时衬底的一侧; 将有源层的第二面接合到最终基板的第二步骤; 以及分离有源层和临时衬底的第三步骤; 该方法的特征在于，临时衬底的侧面具有与有源层的第一侧的表面拓扑互补的表面拓扑，使得临时衬底的表面拓扑封装有源层的第一侧的表面拓扑结构 接合第一步中的层。

公开(公告)号：US12272540B2

公开(公告)日：2025-04-08

申请号：US18470975

申请日：2023-09-20

Applicant: Soitec

Inventor： Pascal Guenard ,  Marcel Broekaart ,  Thierry Barge

IPC: H01L21/02 ,  H10N30/072 ,  H10N30/50 ,  H10N30/853 ,  H03H9/02

Abstract: A method for manufacturing a substrate includes the following steps: (a) providing a support substrate with a first coefficient of thermal expansion, having on one of its faces a first plurality of trenches parallel to each other in a first direction, and a second plurality of trenches parallel to each other in a second direction; (b) transferring a useful layer from a donor substrate to the support substrate, the useful layer having a second coefficient of thermal expansion; wherein an intermediate layer is inserted between the front face of the support substrate and the useful layer, the intermediate layer having a coefficient of thermal expansion between the first and second coefficients of thermal expansion.

公开(公告)号：US11800803B2

公开(公告)日：2023-10-24

申请号：US16306822

申请日：2017-05-30

Applicant: Soitec

Inventor： Marcel Broekaart

IPC: H01L41/312 ,  H01L41/08 ,  H03H3/10 ,  H03H9/02 ,  H10N30/072 ,  H10N30/00

CPC classification number: H10N30/072 ,  H03H3/10 ,  H03H9/02543 ,  H03H9/02574 ,  H10N30/1051 ,  H10N30/10516

Abstract: A hybrid structure for a surface acoustic wave device comprises a useful layer of piezoelectric material having a first free surface and a second surface disposed on a support substrate that has a lower coefficient of thermal expansion than that of the useful layer, wherein the useful layer comprises an area of nanocavities.

公开(公告)号：US20220301847A1

公开(公告)日：2022-09-22

申请号：US17805206

申请日：2022-06-02

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frédéric Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.