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公开(公告)号：US10222415B2
公开(公告)日：2019-03-05
申请号：US15375542
申请日：2016-12-12
Applicant: STMicroelectronics International N.V.
Inventor： Tejinder Kumar , Suchi Prabhu Tandel , Rakesh Malik
IPC: G01R31/317 , G01R31/3193
Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
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公开(公告)号：US10198331B2
公开(公告)日：2019-02-05
申请号：US15475277
申请日：2017-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Tejinder Kumar , Rakesh Malik
IPC: G06F11/22 , G06F11/263 , G06F11/273 , G06F11/07
Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.
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3.发明授权公开(公告)号：US10572440B2
公开(公告)日：2020-02-25
申请号：US15850535
申请日：2017-12-21
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tejinder Kumar , Rathod Ronak Kishorbhai , Apurva Sen , Rakesh Malik
IPC: G06F16/90 , G06F15/78 , G06F16/903
Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.
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公开(公告)号：US10404278B2
公开(公告)日：2019-09-03
申请号：US15381516
申请日：2016-12-16
Applicant: STMicroelectronics International N.V.
Inventor： Tejinder Kumar , Rakesh Malik
Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
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公开(公告)号：US20180337685A1
公开(公告)日：2018-11-22
申请号：US15600152
申请日：2017-05-19
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Vivek Tripathi , Anil Kumar , Rakesh Malik
CPC classification number: H03M1/0872 , H03M1/0663 , H03M1/66 , H03M1/742
Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
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Patent Agency Ranking
6.发明授权Adaptive delay based asynchronous successive approximation analog-to-digital converter 有权基于自适应延迟的异步逐次逼近模数转换器公开(公告)号：US09258008B2
公开(公告)日：2016-02-09
申请号：US14230370
申请日：2014-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Ashish Sharma Kumar , Chandrajit Debnath , Rakesh Malik
CPC classification number: H03M1/125 , H03M1/00 , H03M1/0612 , H03M1/069 , H03M1/0695 , H03M1/12 , H03M1/46 , H03M1/462
Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
Abstract translation: 异步SAR ADC，以高效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。
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公开(公告)号：US20180175883A1
公开(公告)日：2018-06-21
申请号：US15381516
申请日：2016-12-16
Applicant: STMicroelectronics International N.V.
Inventor： Tejinder Kumar , Rakesh Malik
CPC classification number: H03M13/091 , G06F11/1004 , H03M13/6505
Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
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公开(公告)号：US09379728B1
公开(公告)日：2016-06-28
申请号：US14751456
申请日：2015-06-26
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Shiva Sharath Babu Kaleru , Ankur Bal , Mohit Singh , Rakesh Malik
CPC classification number: H03M1/1023 , H03M1/1047 , H03M1/66
Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.
Abstract translation: 一个数模转换器有一个输出。 模拟 - 数字转换器感测数模转换器输出端的电压，并产生一个数字电压信号。 源不匹配估计器处理数字电压信号以输出指示数模转换器内的电流源失配的误差信号。 错误代码发生器从误差信号产生数字校准信号。 数字校准信号由冗余数模转换器转换为模拟补偿信号，以应用于模数转换器的输出，以消除电流源不匹配的影响。
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9.发明申请ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER 审中-公开基于自适应延迟的异步连续逼近模拟数字转换器公开(公告)号：US20160056830A1
公开(公告)日：2016-02-25
申请号：US14930708
申请日：2015-11-03
Applicant: STMicroelectronics International N.V.
Inventor： Rakesh Malik , Chandrajit Debnath , Ashish Sharma Kumar , Pratap Narayan Singh
CPC classification number: H03M1/125 , H03M1/00 , H03M1/0612 , H03M1/069 , H03M1/0695 , H03M1/12 , H03M1/46 , H03M1/462
Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。
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公开(公告)号：US10148277B1
公开(公告)日：2018-12-04
申请号：US15600152
申请日：2017-05-19
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Vivek Tripathi , Anil Kumar , Rakesh Malik
Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.
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