公开(公告)号：US20220416743A1

公开(公告)日：2022-12-29

申请号：US17839335

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Mario MAIORE ,  Tiziano CHIARILLO

IPC: H03F3/70 ,  G01R27/26

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

公开(公告)号：US20240275347A1

公开(公告)日：2024-08-15

申请号：US18634675

申请日：2024-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Mario MAIORE ,  Tiziano CHIARILLO

IPC: H03F3/70 ,  G01R27/26 ,  H03F3/45

CPC classification number: H03F3/70 ,  G01R27/2605 ,  H03F3/45968 ,  H03F2200/375

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

公开(公告)号：US20180313699A1

公开(公告)日：2018-11-01

申请号：US15957999

申请日：2018-04-20

Applicant: STMicroelectronics S.r.l.

Inventor： Michele VAIANA ,  Paolo PESENTI ,  Mario CHIRICOSTA ,  Calogero Marco IPPOLITO ,  Mario MAIORE

IPC: G01K3/14 ,  H03H17/02 ,  G01K7/02

CPC classification number: G01K3/14 ,  G01K7/02 ,  G01K7/021 ,  H03H17/02 ,  H03M3/43 ,  H03M3/456 ,  H03M3/458

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

公开(公告)号：US20160347606A1

公开(公告)日：2016-12-01

申请号：US14962945

申请日：2015-12-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giuseppe BRUNO ,  Sebastiano CONTI ,  Mario CHIRICOSTA ,  Michele VAIANA ,  Calogero Marco IPPOLITO ,  Mario MAIORE ,  Daniele CASELLA

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B7/02 ,  B81B2201/0264 ,  B81B2201/0292 ,  B81B2207/094 ,  G01L19/0092 ,  G01N27/223 ,  H01L23/3121 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.

Abstract translation: 包装传感器组件包括：具有至少一个开口的包装结构; 湿度传感器和压力传感器，其容纳在包装结构内并通过开口与外部流体连通;以及控制电路，可操作地耦合到湿度传感器和压力传感器; 其中所述湿度传感器和所述控制电路集成在第一芯片中，并且所述压力传感器集成在与所述第一芯片不同的第二芯片中并且被结合到所述第一芯片。