公开(公告)号：US20220417076A1

公开(公告)日：2022-12-29

申请号：US17845860

申请日：2022-06-21

Applicant: STMicroelectronics S.r.l.

Inventor： Valerio BENDOTTI ,  Nicola DE CAMPO ,  Carlo CURINA

IPC: H04L27/36 ,  H04L25/40 ,  H03K17/687 ,  H03K19/21 ,  H03K19/096

Abstract: A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.

公开(公告)号：US20230216717A1

公开(公告)日：2023-07-06

申请号：US18146872

申请日：2022-12-27

Applicant: STMicroelectronics S.r.l.

Inventor： Valerio BENDOTTI ,  Valerio GENNARI SANTORI

IPC: H04L27/20 ,  H03K19/20 ,  H04B1/16 ,  H04B1/04 ,  H04L25/49

CPC classification number: H04L27/20 ,  H03K19/20 ,  H04B1/16 ,  H04B1/0466 ,  H04L25/4902

Abstract: An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.

公开(公告)号：US20240178835A1

公开(公告)日：2024-05-30

申请号：US18508011

申请日：2023-11-13

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Carlo CURINA ,  Valerio BENDOTTI

IPC: H03K17/605 ,  H03K3/037 ,  H03K5/133 ,  H03K19/096

CPC classification number: H03K17/605 ,  H03K3/037 ,  H03K5/133 ,  H03K19/096

Abstract: In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.

公开(公告)号：US20230043943A1

公开(公告)日：2023-02-09

申请号：US17870173

申请日：2022-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola ERRICO ,  Valerio BENDOTTI ,  Luca FINAZZI ,  Gaudenzia BAGNATI

IPC: H03K17/16 ,  H02M3/158

Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.

公开(公告)号：US20230266382A1

公开(公告)日：2023-08-24

申请号：US17678772

申请日：2022-02-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Gaudenzia BAGNATI ,  Stefano CASTORINA ,  Valerio BENDOTTI

IPC: G01R31/28 ,  H03K17/687 ,  H03K5/24 ,  G01R31/54 ,  G01R19/165

CPC classification number: G01R31/2851 ,  H03K17/6874 ,  H03K5/24 ,  G01R31/54 ,  G01R19/16571 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.