公开(公告)号：US20240045589A1

公开(公告)日：2024-02-08

申请号：US18488581

申请日：2023-10-17

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20230206032A1

公开(公告)日：2023-06-29

申请号：US18172979

申请日：2023-02-22

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Giuseppe DESOLI ,  Carmine CAPPETTA ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Saumya SUNEJA

IPC: G06N3/045 ,  G06F16/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/21

CPC classification number: G06N3/045 ,  G06F16/2282 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F18/217

Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.

公开(公告)号：US20220269410A1

公开(公告)日：2022-08-25

申请号：US17742987

申请日：2022-05-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US20210241806A1

公开(公告)日：2021-08-05

申请号：US17158875

申请日：2021-01-26

Applicant: STMicroelectronics International N.V. ,  STMICROELECTRONICS S.r.l.

Inventor： Nitin CHAWLA ,  Thomas BOESCH ,  Anuj Grover ,  Surinder Pal SINGH ,  Giuseppe DESOLI

IPC: G11C8/04 ,  G06N3/02

Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

公开(公告)号：US20180189215A1

公开(公告)日：2018-07-05

申请号：US15423289

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F13/40 ,  G06F9/445 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F17/505 ,  G06F17/5054 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0472 ,  G06N3/084 ,  G06N7/005 ,  G06N20/10

Abstract: Embodiments are directed towards a reconfigurable stream switch formed in an integrated circuit. The stream switch includes a plurality of output ports, a plurality of input ports, and a plurality of selection circuits. The output ports each have an output port architectural composition, and each is arranged to unidirectionally pass output data and output control information. The input ports each have an input port architectural composition, and each is arranged to unidirectionally receive first input data and first input control information. Each one of the selection circuits is coupled to an associated one of the output ports. Each selection circuit is further coupled to all of the input ports such that each selection circuit is arranged to reconfigurably couple its associated output port to no more than one input port at any given time.

公开(公告)号：US20230350483A1

公开(公告)日：2023-11-02

申请号：US18338950

申请日：2023-06-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G05F3/24 ,  G11C11/413 ,  G06F1/3234 ,  G06F1/3287 ,  G06F15/78

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20230186067A1

公开(公告)日：2023-06-15

申请号：US18167366

申请日：2023-02-10

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/063 ,  G06T7/62 ,  G06T7/11 ,  G06F16/901 ,  G06F9/38 ,  G06N3/08 ,  G06T15/08 ,  G06V10/82 ,  G06F18/22 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06T7/62 ,  G06T7/11 ,  G06F16/9024 ,  G06F9/3877 ,  G06N3/08 ,  G06T15/08 ,  G06V10/82 ,  G06F18/22 ,  G06N3/045

Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

公开(公告)号：US20230135185A1

公开(公告)日：2023-05-04

申请号：US18055245

申请日：2022-11-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/063 ,  G06F17/18 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US20220027715A1

公开(公告)日：2022-01-27

申请号：US17383132

申请日：2021-07-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Diego CARRERA ,  Matteo COLELLA ,  Giuseppe DESOLI ,  Giacomo BORACCHI ,  Beatrice ROSSI ,  Pasqualina FRAGNETO ,  Luca FRITTOLI

IPC: G06N3/063 ,  G06N3/04 ,  G06K9/62

Abstract: A method, comprising: providing an ANN processing stage having a plurality of processing layers with respective parameters including at least one set of weight parameters, at least one input, resp. output, activation parameter and at least one activation function parameter; setting to an integer value a dimensional parameter of a lattice having a plurality of lattice points and identified by a set of basis vectors; selecting a set of weight parameters of a respective processing layer; vectorizing the selected set of weight parameters producing a set of weight vectors arranged as items of a matrix of weight vectors; normalizing the matrix of weight vectors; applying lattice vector quantization, LVQ, processing to the matrix of normalized weight vectors, producing a codebook of codewords; indexing by encoding codewords of the codebook as a function of the lattice, producing respective tuples of indices. The normalization comprises solving an optimization problem having a first term configured to provide normalized weight values approximating at least output, as a function of at least one input, activation parameter, and a regularization term ΩL, configured to amplify weight values having a short distance from the lattice points of the lattice L.

公开(公告)号：US20210264250A1

公开(公告)日：2021-08-26

申请号：US16799671

申请日：2020-02-24

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/08 ,  G06N3/04 ,  G06F17/18 ,  G06K9/62

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.