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公开(公告)号：US11442142B2
公开(公告)日：2022-09-13
申请号：US16795977
申请日：2020-02-20
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Egidio Ragonese , Claudio Nocera , Alessandro Finocchiaro , Giuseppe Palmisano
Abstract: An input receives a radio frequency (RF) signal having an interfering component superimposed thereon. The RF signal is mixed with a local oscillator (LO) signal and down-converted to an intermediate frequency (IF) to generate a mixed signal which includes a frequency down-converted interfering component. The mixed signal is amplified by an amplifier to generate an output signal. A feedback loop processes the output signal to generate a correction signal for cancelling the frequency down-converted interfering component at the input of the amplifier. The feedback loop includes a low-pass filter and a amplification circuit which outputs the correction signal.
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公开(公告)号：US12210089B2
公开(公告)日：2025-01-28
申请号：US18418298
申请日：2024-01-21
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
Abstract: A flash analog-to-digital converter (ADC) receives an input control signal and performs coarse tuning of a frequency of an output signal, produced between first and second nodes having an inductance coupled therebetween. The flash ADC quantizes an operating frequency range for the output signal produced between the first and second nodes as M·Δf, where M is an integer from 0 to N−1, where N is a number of intervals into which a frequency range for the output signal is divided, and where Δf is a resulting frequency step produced by the quantizing. The value of M is generated based upon the input control signal and a word controlling switches of a plurality of switched capacitance circuits associated with the first and second nodes to close ones of those switches associated with the control word to coarsely tune the frequency of the output signal.
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公开(公告)号：US20230018212A1
公开(公告)日：2023-01-19
申请号：US17838159
申请日：2022-06-10
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Andrea Cavarra , Giuseppe Palmisano
IPC: H03K5/00 , H03F3/20 , G01S13/931
Abstract: In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.
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公开(公告)号：US11959995B2
公开(公告)日：2024-04-16
申请号：US17395080
申请日：2021-08-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Finocchiaro , Alessandro Parisi , Andrea Cavarra , Giuseppe Papotto , Giuseppe Palmisano
IPC: G01S13/34 , G01S13/931 , H03B5/12 , H03L7/193 , G01S13/00
CPC classification number: G01S13/34 , G01S13/931 , H03B5/1231 , H03L7/193
Abstract: A PLL has a tunable resonator including an inductance and variable capacitance coupled between first and second nodes, and capacitances coupleable between the nodes. A control node is coupled to the variable capacitance and receives a control signal for tuning the resonator. A biasing circuit biases the resonator to generate an output. A PFD circuit senses timing offset of the output with respect to a reference and asserts first or second digital signals dependent on the sign of the timing offset. A charge pump generates the control signal based on the first and second digital signals. A timer asserts a timing signal in response to a pulse sensed in a reset signal and de-asserts the timing signal after a time interval. A calibrator couples selected capacitances between the first and second nodes as a function of the second digital signal, in response to assertion of the timing signal.
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公开(公告)号：US11879963B2
公开(公告)日：2024-01-23
申请号：US18108993
申请日：2023-02-13
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
CPC classification number: G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03L7/193
Abstract: Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
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Patent Agency Ranking
公开(公告)号：US12224754B2
公开(公告)日：2025-02-11
申请号：US17838159
申请日：2022-06-10
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Andrea Cavarra , Giuseppe Palmisano
IPC: H03K5/00 , G01S13/931 , H03F3/20
Abstract: A circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.
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公开(公告)号：US11604267B2
公开(公告)日：2023-03-14
申请号：US17395016
申请日：2021-08-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Parisi , Andrea Cavarra , Alessandro Finocchiaro , Giuseppe Papotto , Giuseppe Palmisano
Abstract: An oscillator includes a tunable resonant circuit having an inductance and a variable capacitance coupled between first and second nodes, and a set of capacitances selectively coupleable between the first and second nodes. An input control node receiving an input control signal is coupled to the variable capacitance and set of capacitances. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable-frequency output signal between the first and second nodes. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits with hysteresis compares the input control signal to the set of different voltage thresholds to generate a set of control signals. The capacitances in the set of capacitances are selectively coupleable between the first and second nodes as a function of control signals in the set of control signals.
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公开(公告)号：US11689156B1
公开(公告)日：2023-06-27
申请号：US17643068
申请日：2021-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Alessandro Parisi , Andrea Cavarra , Giuseppe Palmisano
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1215 , H03B5/1265 , H03B2200/004
Abstract: A voltage controlled oscillator (VCO) includes: a pair of inductors coupled in series; a first pair of varactors coupled in series, and a second pair of varactors coupled in series. A first common mode node is between the respective varactors of the first pair of varactors and a second common mode node is between the respective varactors of the second pair of varactors. A supply voltage node is switchably coupled to the first common mode node through a first switch, the supply voltage node being a node located between the pair of inductors. A control voltage node (VC) is switchably coupled to the second common mode node through a second switch.
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公开(公告)号：US20230179147A1
公开(公告)日：2023-06-08
申请号：US17643068
申请日：2021-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Giuseppe Papotto , Alessandro Parisi , Andrea Cavarra , Giuseppe Palmisano
IPC: H03B5/12
CPC classification number: H03B5/124 , H03B5/1215 , H03B5/1265 , H03B2200/004
Abstract: A voltage controlled oscillator (VCO) includes: a pair of inductors coupled in series; a first pair of varactors coupled in series, and a second pair of varactors coupled in series. A first common mode node is between the respective varactors of the first pair of varactors and a second common mode node is between the respective varactors of the second pair of varactors. A supply voltage node is switchably coupled to the first common mode node through a first switch, the supply voltage node being a node located between the pair of inductors. A control voltage node (Vc) is switchably coupled to the second common mode node through a second switch.
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10.发明授权System for the correction of the phase error of two in-phase and quadrature signals, corresponding device and method 有权用于校正两个同相和正交信号的相位误差的系统，相应的装置和方法公开(公告)号：US09479208B2
公开(公告)日：2016-10-25
申请号：US14751470
申请日：2015-06-26
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Giuseppe Papotto , Giuseppe Palmisano
CPC classification number: H04B1/16 , H03F3/24 , H03K5/1565 , H04L27/364 , H04W56/0035 , H04W56/005
Abstract: A system for correction of the phase error in in-phase and quadrature signals may include a first signal and a second signal. The system includes a first circuit and a second circuit, each circuit configured for receiving a square-wave input signal and supplying a respective square-wave output signal. The output signal is delayed with respect to the input signal and each circuit is configured in such a way that the propagation delay of a rising edge and the propagation delay of a falling edge between the input signal and the output signal are configurable. The first circuit is configured for receiving the first signal, and the second circuit is configured for receiving the second signal.
Abstract translation: 用于校正同相和正交信号中的相位误差的系统可以包括第一信号和第二信号。 该系统包括第一电路和第二电路，每个电路被配置为接收方波输入信号并提供相应的方波输出信号。 输出信号相对于输入信号被延迟，并且每个电路被配置成使得输入信号和输出信号之间的上升沿的传播延迟和下降沿的传播延迟是可配置的。 第一电路被配置为接收第一信号，并且第二电路被配置为接收第二信号。
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