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    TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME
    2.
    发明申请
    TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME 审中-公开
    具有低K侧壁间隔器的晶体管及其制造方法

    公开(公告)号：US20160343814A1

    公开(公告)日：2016-11-24

    申请号：US15227182

    申请日：2016-08-03

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Clement Gaumer ,  Daniel Benoit

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45

    CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/78

    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

    Abstract translation: 通过在半导体层的顶部上限定栅极叠层来形成晶体管。 栅极堆叠包括栅极电介质和栅电极。 具有第一介电常数的第一介电材料层沉积在栅极堆叠的侧壁上以形成牺牲侧壁间隔物。 然后在邻近牺牲侧壁间隔物的栅极堆叠的每一侧外延生长凸起的源极 - 漏极区域。 然后去除牺牲侧壁间隔物，以在每个凸起的源极 - 漏极区域和栅极堆叠之间产生开口。 然后将具有小于第一介电常数的第二介电常数的第二介电材料层沉积在栅极堆叠的开口和侧壁中以形成低k侧壁间隔物。

    Method for manufacturing insulated-gate MOS transistors
    3.
    发明授权
    Method for manufacturing insulated-gate MOS transistors 有权
    绝缘栅MOS晶体管的制造方法

    公开(公告)号：US08878331B2

    公开(公告)日：2014-11-04

    申请号：US13659771

    申请日：2012-10-24

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Mickael Gros-Jean ,  Clement Gaumer ,  Emmanuel Bayard Perrin

    IPC: H01L29/02 ,  H01L21/70 ,  H01L21/28 ,  H01L29/51 ,  H01L21/762 ,  H01L21/8234

    CPC classification number: H01L21/76232 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

    Abstract translation: 一种用于在半导体衬底中限定绝缘体的方法包括在衬底中形成沟槽，在沟槽中形成其上表面布置在衬底表面上方的绝缘材料，并在绝缘材料的一部分中形成扩散阻挡层 位于半导体衬底的表面上方。 这样的绝缘体可以用于例如绝缘并描绘形成在基板中的电子部件或部件。

    Transistor with a low-k sidewall spacer and method of making same
    4.
    发明授权
    Transistor with a low-k sidewall spacer and method of making same 有权
    具有低k侧壁间隔物的晶体管及其制造方法

    公开(公告)号：US09437694B1

    公开(公告)日：2016-09-06

    申请号：US14676369

    申请日：2015-04-01

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Clement Gaumer ,  Daniel Benoit

    IPC: H01L21/8232 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/78

    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

    Abstract translation: 通过在半导体层的顶部上限定栅极叠层来形成晶体管。 栅极堆叠包括栅极电介质和栅电极。 具有第一介电常数的第一介电材料层沉积在栅极堆叠的侧壁上以形成牺牲侧壁间隔物。 然后在邻近牺牲侧壁间隔物的栅极堆叠的每一侧外延生长凸起的源极 - 漏极区域。 然后去除牺牲侧壁间隔物，以在每个凸起的源极 - 漏极区域和栅极堆叠之间产生开口。 然后将具有小于第一介电常数的第二介电常数的第二介电材料层沉积在栅极堆叠的开口和侧壁中以形成低k侧壁间隔物。

    METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS
    5.
    发明申请
    METHOD FOR MANUFACTURING INSULATED-GATE MOS TRANSISTORS 有权
    制造绝缘栅MOS晶体管的方法

    公开(公告)号：US20130099329A1

    公开(公告)日：2013-04-25

    申请号：US13659771

    申请日：2012-10-24

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Mickael Gros-Jean ,  Clement Gaumer ,  Emmanuel Bayard Perrin

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L21/76232 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

    Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

    Abstract translation: 一种用于在半导体衬底中限定绝缘体的方法包括在衬底中形成沟槽，在沟槽中形成其上表面布置在衬底表面上方的绝缘材料，并在绝缘材料的一部分中形成扩散阻挡层 位于半导体衬底的表面上方。 这样的绝缘体可以用于例如绝缘并描绘形成在基板中的电子部件或部件。

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