公开(公告)号：US20240170434A1

公开(公告)日：2024-05-23

申请号：US18193012

申请日：2023-03-30

Applicant: AG MATERIALS TECHNOLOGY CO., LTD.

Inventor： Chien-Hsun CHUANG

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29171

Abstract: A back side metallization thin film structure is provided, which includes a wafer and a metallic nano-twinned thin film on the back side of the wafer. A plurality of integrated circuit devices are formed on the front side of the wafer. The metallic nano-twinned thin film includes silver, copper, gold, palladium, or nickel. The metallic nano-twinned thin film has a transition layer near the wafer and a twin layer away from the wafer. The twin layer accounts for at least 70% of the thickness of the metallic nano-twinned thin film and includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include more than 50% of (111) crystal orientation. The back side metallization thin film structure is formed by activating the wafer surface by ion beam bombardment, followed by an evaporation deposition process performed on the activated wafer surface with simultaneous ion beam bombardment.

公开(公告)号：US20240113066A1

公开(公告)日：2024-04-04

申请号：US18264719

申请日：2022-01-28

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Takashi IMAHIGASHI

IPC: H01L23/00 ,  H01S5/0234 ,  H01S5/026

CPC classification number: H01L24/73 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01S5/0234 ,  H01S5/0261 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/1145 ,  H01L2224/11466 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/2745 ,  H01L2224/27466 ,  H01L2224/2747 ,  H01L2224/27848 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29169 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2924/01203 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/1426

Abstract: An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.

公开(公告)号：US20240096823A1

公开(公告)日：2024-03-21

申请号：US18520337

申请日：2023-11-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L22/34 ,  H01L23/528 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/49 ,  H01L2224/08237 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/49171 ,  H01L2224/73215

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

公开(公告)号：US11923333B2

公开(公告)日：2024-03-05

申请号：US17690276

申请日：2022-03-09

Applicant: DEXERIALS CORPORATION

Inventor： Yasushi Akutsu

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29082 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/83203 ,  H01L2224/83851

Abstract: An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.

公开(公告)号：US11848284B2

公开(公告)日：2023-12-19

申请号：US17834737

申请日：2022-06-07

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Javier A DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L22/34 ,  H01L23/528 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/49 ,  H01L2224/08237 ,  H01L2224/29082 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/49171 ,  H01L2224/73215

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

公开(公告)号：US11710716B2

公开(公告)日：2023-07-25

申请号：US17738655

申请日：2022-05-06

Applicant: DEXERIALS CORPORATION

Inventor： Seiichiro Shinohara

IPC: B32B37/06 ,  B32B37/10 ,  B32B37/24 ,  B32B38/00 ,  C08G59/68 ,  H01L23/00 ,  H05K3/32 ,  C09J4/00 ,  H05K1/03 ,  B32B3/26 ,  B32B37/00

CPC classification number: H01L24/29 ,  B32B3/263 ,  B32B37/025 ,  B32B37/06 ,  B32B37/10 ,  B32B37/24 ,  B32B38/0008 ,  C08G59/68 ,  H01L24/27 ,  H01L24/83 ,  H05K3/323 ,  B32B2037/243 ,  B32B2305/30 ,  B32B2307/202 ,  B32B2457/00 ,  C09J4/00 ,  H01L2224/27003 ,  H01L2224/27005 ,  H01L2224/294 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29076 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29357 ,  H01L2224/29364 ,  H01L2224/29499 ,  H01L2224/83851 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0373 ,  H05K2201/0215 ,  Y10T428/24521 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29357 ,  H01L2924/00014 ,  H01L2224/29355 ,  H01L2924/00014 ,  H01L2224/29347 ,  H01L2924/00014 ,  H01L2224/29344 ,  H01L2924/00014 ,  H01L2224/29364 ,  H01L2924/00014 ,  H01L2224/2939 ,  H01L2924/00014 ,  H01L2224/294 ,  H01L2924/00014 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: An anisotropic conductive film has a three-layer structure in which a first connection layer is sandwiched between a second connection layer and a third connection layer that each are formed mainly of an insulating resin. The first connection layer has a structure in which conductive particles are arranged in a single layer in the plane direction of an insulating resin layer on a side of the second connection layer, and the thickness of the insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than that of the insulating resin layer in regions in proximity to the conductive particles.

公开(公告)号：US20190214525A1

公开(公告)日：2019-07-11

申请号：US15754959

申请日：2016-08-23

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Barbara Behr ,  Andreas Weimar ,  Mathias Wendt ,  Marcus Zenger

IPC: H01L33/00 ,  H01L33/62 ,  H01L23/00

CPC classification number: H01L33/0079 ,  H01L24/29 ,  H01L24/30 ,  H01L24/33 ,  H01L24/83 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/30505 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/83805 ,  H01L2224/8381 ,  H01L2924/3511

Abstract: A device and a method for producing a device are disclosed. In an embodiment the device includes a first component; a second component; and a connecting element arranged between the first component and the second component, wherein the connecting element comprises at least a first phase and a second phase, wherein the first phase comprises a first metal having a first concentration, a second metal having a second concentration and a third metal having a third concentration, wherein the second phase comprises the first metal having a fourth concentration, the second metal and the third metal, wherein the first metal, the second metal and the third metal are different from one another and are suitable for reacting at a processing temperature of less than 200° C., and wherein the following applies: c11≥c25 and c11 ≥c13≥c12.

公开(公告)号：US10074583B2

公开(公告)日：2018-09-11

申请号：US14927989

申请日：2015-10-30

Applicant: International Business Machines Corporation

Inventor： Akihiro Horibe ,  Sayuri Hada ,  Kuniaki Sueoka

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/26145 ,  H01L2224/27002 ,  H01L2224/27013 ,  H01L2224/29082 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00014

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

公开(公告)号：US10039194B2

公开(公告)日：2018-07-31

申请号：US14415676

申请日：2013-08-01

Applicant: OSRAM SYLVANIA Inc.

Inventor： Jeffery Serre ,  Alan Lenef ,  Adam Scotch

IPC: H05K3/34 ,  B23K3/06 ,  B23K1/00 ,  B23K1/20 ,  H05K1/11 ,  H05K13/04 ,  H01L23/00 ,  H01L33/62

CPC classification number: H05K3/3431 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/0684 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L33/62 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29113 ,  H01L2224/325 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/8321 ,  H01L2224/83815 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/95085 ,  H01L2224/95101 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2924/01322 ,  H05K1/111 ,  H05K3/3468 ,  H05K13/0465 ,  H05K2201/10992 ,  H05K2203/044 ,  H05K2203/047 ,  H05K2203/048 ,  H01L2924/00012 ,  H01L2924/0105

Abstract: A dual solder layer for fluidic self assembly, an electrical component substrate, and method employing same is described. The dual solder layer comprises a layer of a self-assembly solder disposed on a layer of a base solder which is disposed on the solder pad of an electrical component substrate. The self-assembly solder has a liquidus temperature less than a first temperature and the base solder has a solidus temperature greater than the first temperature. The self-assembly solder liquefies at the first temperature during a fluidic self assembly method to cause electrical components to adhere to the substrate. After attachment, the substrate is removed from the bath and heated so that the base solder and self-assembly solder combine to form a composite alloy which forms the final electrical solder connection between the component and the solder pad on the substrate.

公开(公告)号：US20180158759A1

公开(公告)日：2018-06-07

申请号：US15883151

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Georg MEYER-BERG

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/24155 ,  H01L2224/29082 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1715 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/17763 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/20647 ,  H01L2924/20648 ,  H01L2924/20649 ,  H01L2924/2065 ,  H01L2924/00

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.