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公开(公告)号：US12212866B2
公开(公告)日：2025-01-28
申请号：US18500449
申请日：2023-11-02
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent Simony
Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
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公开(公告)号：US20240064427A1
公开(公告)日：2024-02-22
申请号：US18500449
申请日：2023-11-02
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent Simony
IPC: H04N25/709 , H04N25/77 , H02M3/155
CPC classification number: H04N25/709 , H04N25/77 , H02M3/155
Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
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公开(公告)号：US11856307B2
公开(公告)日：2023-12-26
申请号：US18052478
申请日：2022-11-03
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent Simony
IPC: H04N25/709 , H04N25/77 , H02M3/155 , G05F1/575 , H01L29/786 , H03M1/08
CPC classification number: H04N25/709 , H02M3/155 , H04N25/77
Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
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Patent Agency Ranking
公开(公告)号：US20230145151A1
公开(公告)日：2023-05-11
申请号：US18052478
申请日：2022-11-03
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent Simony
IPC: H04N25/709 , H02M3/155 , H04N25/77
CPC classification number: H04N25/709 , H02M3/155 , H04N25/77
Abstract: In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
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公开(公告)号：US11451730B2
公开(公告)日：2022-09-20
申请号：US16890877
申请日：2020-06-02
Inventor： Pierre Malinge , Frederic Lalanne , Laurent Simony
IPC: H04N5/3745 , H04N5/355
Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.
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公开(公告)号：US11094726B2
公开(公告)日：2021-08-17
申请号：US16829837
申请日：2020-03-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent Simony
IPC: H01L27/146 , H04N5/369
Abstract: A global shutter pixel includes a first transistor and a first switch series-connected between a first node of application of a potential and an internal node of the pixel. A control terminal of the first transistor is coupled to a floating diffusion node of the pixel. At least two assemblies are coupled to the internal node, where each assembly is formed of a capacitor series-connected with a second switch coupling the capacitor to the internal node. A second transistor has a control terminal connected to the internal node and a first conduction terminal coupled to an output node of the pixel. The pixel operation is controlled to store an initialization voltage from the floating diffusion on one of the capacitors and a pixel integration voltage from the floating diffusion on another of the capacitors.
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公开(公告)号：US11212475B2
公开(公告)日：2021-12-28
申请号：US16890944
申请日：2020-06-02
Inventor： Laurent Simony , Pierre Malinge
Abstract: A sensor includes pixels each including: a first transistor and a first switch in series between a first node and an internal node of the pixel, a gate of the first transistor being coupled to a second node; a capacitive element, a first terminal of which is connected to the second node; and a plurality of assemblies each including a capacitance in series with a second switch coupled to the internal node. The sensor includes a circuit configured to control, each time a voltage is stored in one of the assemblies, the interruption of a current between the first node and the internal node: by switching a first potential applied to a second terminal of the capacitive element; or by opening the first switch.
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公开(公告)号：US09473160B2
公开(公告)日：2016-10-18
申请号：US14835980
申请日：2015-08-26
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Laurent Simony
CPC classification number: H03M1/20 , H01L27/14643 , H03M1/002 , H03M1/0604 , H03M1/188 , H03M1/36 , H03M1/56
Abstract: A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2n-m times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.
Abstract translation: 一种方法包括通过m比特的模拟信号的第一模拟/数字转换，具有与第一满量程值相关联的m小于n的模拟信号，以及在与第二满量程相关联的m位上的模拟信号的第二模拟/数字转换 全尺寸值比第一大2n-m倍。 两个模拟/数字转换同时执行，分别传送m位的第一中间数字字和m位的第二中间数字字。 该方法还包括在两个模拟/数字转换之后执行的数字后处理，并产生从扩展到n位的两个中间数字字中的至少一个开始的n位数字字，以及从至少一个阈值数字指示代表 的至少一个阈值小于或等于第一满量程值。
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