公开(公告)号：US20240297043A1

公开(公告)日：2024-09-05

申请号：US18583758

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Alfio GUARNERA ,  Cateno Marco CAMALLERI ,  Edoardo ZANETTI ,  Laura Letizia SCALIA ,  Mario Pietro BERTOLINI ,  Massimiliano CANTIANO ,  Massimo BOSCAGLIA ,  Mario Giuseppe SAGGIO

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/046 ,  H01L29/0619 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7802

Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.

公开(公告)号：US20240297249A1

公开(公告)日：2024-09-05

申请号：US18583748

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Edoardo ZANETTI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/0465 ,  H01L29/0603 ,  H01L29/1608

Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.

公开(公告)号：US20240297044A1

公开(公告)日：2024-09-05

申请号：US18583752

申请日：2024-02-21

Applicant: STMicroelectronics International N.V.

Inventor： Cateno Marco CAMALLERI ,  Mario Giuseppe SAGGIO ,  Edoardo ZANETTI ,  Gabriele BELLOCCHI

IPC: H01L21/04

CPC classification number: H01L21/0465

Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.

公开(公告)号：US20250043460A1

公开(公告)日：2025-02-06

申请号：US18779699

申请日：2024-07-22

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Cateno Marco CAMALLERI ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Alessia Maria FRAZZETTO

IPC: C30B25/20 ,  C30B29/36 ,  C30B33/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A manufacturing process vertical-conduction power device includes: from a layer containing semiconductor material with a lattice structure having spatial symmetry, growing an epitaxial layer, having the lattice structure with spatial symmetry and a first electrical conductivity; forming body having regions a second electrical conductivity, opposite to the first electrical conductivity, in the epitaxial layer; and forming a current-spreading layer in the epitaxial layer between the body regions. Forming the body regions includes carrying out a body channeling ion implantation, using a body mask. Forming the current-spreading layer includes: forming shallow damaged regions in the body regions through the body mask so that the lattice structure is altered in the shallow damaged regions; and carrying out a current-spreading channeling ion implantation, using the shallow damaged regions as implantation mask.

公开(公告)号：US20240258422A1

公开(公告)日：2024-08-01

申请号：US18396524

申请日：2023-12-26

Applicant: STMicroelectronics International N.V.

Inventor： Cateno Marco CAMALLERI ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/66712

Abstract: The present disclosure is directed to a MOSFET device including a semiconductor body with: a plurality of source regions of a first conductivity type; a plurality of body regions of a second conductivity type, which form a plurality of channel regions; and a drain region of the first conductivity type. The MOSFET device further includes a plurality of insulated gate regions, each of which includes a respective gate conductive region and a respective gate dielectric region, which is partially interposed between the gate conductive region and corresponding source regions and is also partially interposed between the gate conductive region and corresponding channel regions. The MOSFET device further includes a plurality of barrier structures, each of which extends on a corresponding insulated gate region and includes at least one respective first barrier region of silicon nitride.

公开(公告)号：US20240258377A1

公开(公告)日：2024-08-01

申请号：US18408474

申请日：2024-01-09

Applicant: STMicroelectronics International N.V.

Inventor： Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Laura Letizia SCALIA ,  Alfio GUARNERA

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L21/0465 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

Abstract: A MOSFET device of a vertical conduction type has a substrate of silicon carbide having a first conductivity type and a main face. A body region of a second conductivity type extends into the substrate from the main face and has a first depth along a first direction. A first and a second source region of the first conductivity type extend inside the body region starting from the main face parallel to each other and have a second depth along the first direction smaller than the first depth and are mutually spaced by a distance in a second direction perpendicular to the first direction. A body contact region of the second conductivity type extends inside the body region between the first and the second source regions and has a third depth along the first direction greater than or equal to the second depth.