公开(公告)号：US20020082791A1

公开(公告)日：2002-06-27

申请号：US10025372

申请日：2001-12-19

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet

IPC: G06F019/00 ,  G01R035/00

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G11C16/04 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract translation: 用于以接近于持续时间的典型值的值调整集成电路中的内部定时信号的持续时间的方法可以包括激活集成电路中的内部定时信号并且顺序地将校准值发送到集成电路的输入。 内部定时信号的到期可以确定接收或正在接收的最后一个校准值，并且校准数据可以应用于用于调整内部定时信号的持续时间的设备。

公开(公告)号：US20010012191A1

公开(公告)日：2001-08-09

申请号：US09751300

申请日：2000-12-28

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet

IPC: H02H009/00

CPC classification number: H01L27/0266

Abstract: The protection device for an interconnection line of an integrated circuit includes a charge flow-off device connected between the interconnection line to be protected and the substrate of the integrated circuit. The protection device also includes a dummy interconnection line ANT to activate the flow-off device. The protection device is active throughout the manufacture of the integrated circuit.

Abstract translation: 用于集成电路的互连线路的保护装置包括连接在待保护的互连线与集成电路的基板之间的充电流失装置。 保护装置还包括虚拟互连线ANT以激活流失装置。 保护装置在整个集成电路的制造过程中是有效的。

公开(公告)号：US20030035329A1

公开(公告)日：2003-02-20

申请号：US10178796

申请日：2002-06-24

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet ,  Francesco La Rosa

IPC: G11C029/00

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/08

Abstract: An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

Abstract translation: 电可编程和可擦除存储器包括存储单元，其中每个存储单元包括浮栅晶体管和存取晶体管。 浮栅晶体管具有连接到存取晶体管的第一端。 存储器包括用于在擦除阶段期间分别施加第一信号的电路和在要擦除的存储器单元的控制栅极和浮置栅极晶体管的第二端子上的第二信号。 该电路还适用于存储器单元的相应存取晶体管的栅极，以被擦除具有与第一信号的电压不同的电压的信号，并且相对于第二个电压的电压具有低或零电位差 信号。 保护存储器不受存取晶体管栅极氧化物击穿的影响。