公开(公告)号：US20020113643A1

公开(公告)日：2002-08-22

申请号：US09938289

申请日：2001-08-23

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03B001/00

CPC classification number: H03K5/1252

Abstract: A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.

Abstract translation: 滤波电路包括当待滤波的逻辑信号改变值时递送第一和第二斜坡形信号的电路，并且包括各自具有切换阈值的逻辑电路，用于接收斜坡形状的信号。 当逻辑电路的输出具有第一对值时，存储器单元递送具有第一值的输出信号，并且当逻辑电路的输出具有第二对值时传送第二值。 滤波电路可以应用于串行型存储器件中的外部时钟信号的滤波。

公开(公告)号：US20040252568A1

公开(公告)日：2004-12-16

申请号：US10816204

申请日：2004-04-01

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C011/34

CPC classification number: G11C16/26 ,  G11C7/067 ,  G11C2207/063

Abstract: The present invention relates to a sense amplifier for reading a memory cell, comprising a read node linked directly or indirectly to the memory cell, a first active branch connected to the read node, comprising means for supplying a read current at the read node, and a data output linked to one node of the first active branch at which a voltage representative of the conductivity state of the memory cell appears. According to the present invention, the sense amplifier comprises a second active branch connected to the read node, comprising means for supplying, at the read node, a current that is added to the current supplied by the first active branch, such that the voltage representative of the conductivity state of the memory cell remains substantially stable upon a current draw at the read node. Application particularly to reading non-volatile FLASH and EEPROM type memory cells.

Abstract translation: 本发明涉及用于读取存储单元的读出放大器，包括直接或间接地连接到存储单元的读节点，连接到读节点的第一活动分支，包括用于在读节点提供读电流的装置，以及 连接到第一有效分支的一个节点的数据输出，在该节点处表示存储单元的电导率状态的电压。 根据本发明，感测放大器包括连接到读节点的第二有源分支，包括用于在读节点处提供与第一有源分支提供的电流相加的电流的装置，使得电压代表 在读取节点上的电流消耗时，存储单元的导电性状态保持基本稳定。 特别适用于读取非易失性FLASH和EEPROM型存储单元。

公开(公告)号：US20030001228A1

公开(公告)日：2003-01-02

申请号：US10165051

申请日：2002-06-07

Applicant: STMicroelectronics S.A.

Inventor： Philippe Boivin ,  Francesco La Rosa

IPC: H01L029/00

CPC classification number: H01L27/0255 ,  H01L27/0251

Abstract: An integrated circuit on a silicon substrate includes at least one polysilicon line and at least one antistatic contact connecting the polysilicon line to the silicon substrate. The antistatic contact includes a thin oxide layer between the polysilicon line and the silicon substrate. The thin oxide layer is of a sufficiently small thickness so that a current flows across it by the tunnel effect when the polysilicon line is brought, relatively to the substrate, to a voltage greater or less than determined thresholds.

Abstract translation: 硅衬底上的集成电路包括至少一个多晶硅线和将多晶硅线连接到硅衬底的至少一个抗静电接触。 抗静电接触包括在多晶硅线和硅衬底之间的薄氧化层。 薄氧化物层具有足够小的厚度，使得当多晶硅线相对于衬底被带到大于或小于确定的阈值的电压时，电流通过隧道效应流过它。

公开(公告)号：US20010044922A1

公开(公告)日：2001-11-22

申请号：US09737827

申请日：2000-12-15

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03M013/00

CPC classification number: G06F11/1008 ,  G06F11/1032 ,  G06F2201/81 ,  H03M13/19

Abstract: A method for the correction of an erroneous bit in a string of bits includes providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The correct value of the erroneous bit is computed by using the other bits of the string of bits comprising the parity bit. The erroneous bit is then replaced by its correct value. The method is applicable to error correction circuits in EEPROM memories.

Abstract translation: 用于校正一串比特中的错误比特的方法包括：在该比特串中，提供在该错误比特有效的时间点从该比特串的其他比特计算的第一奇偶校验位。 通过使用包括奇偶校验位的位串串的其他位来计算错误位的正确值。 错误的位被其正确的值替换。 该方法适用于EEPROM存储器中的纠错电路。

公开(公告)号：US20030095453A1

公开(公告)日：2003-05-22

申请号：US10299965

申请日：2002-11-19

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: The present invention relates to a read amplifier (SA2) comprising a read stage (RDST), a reference stage (RFST) and a differential output stage comprising PMOS and NMOS type transistors. According to the present invention, the transistors of the differential stage (DIFST2) comprise only one PMOS transistor (TP3) and one NMOS transistor (TN3) in series, the PMOS transistor (TP3) having its gate linked to one node of the read stage (RDST), the NMOS transistor (TN3) having its gate linked to one node of the reference stage (RFST), the mid-point of the PMOS and NMOS transistors of the differential stage forming a data output node (DATAOUT) of the read amplifier. The read amplifier according to the present invention has the combined advantages of a short read time and a low electrical consumption. Application to EPROM, EEPROM and FLASH type non-volatile memories.

Abstract translation: 本发明涉及包括读阶段（RDST），参考级（RFST）和包括PMOS和NMOS型晶体管的差分输出级的读放大器（SA2）。 根据本发明，差分级（DIFST2）的晶体管仅包括串联的一个PMOS晶体管（TP3）和一个NMOS晶体管（TN3），PMOS晶体管（TP3）的栅极连接到读取级的一个节点 （RDST），其栅极连接到参考级（RFST）的一个节点的NMOS晶体管（TN3），差分级的PMOS和NMOS晶体管的中点形成读取的数据输出节点（DATAOUT） 放大器 根据本发明的读取放大器具有短的读取时间和低的电力消耗的组合优点。 应用于EPROM，EEPROM和FLASH型非易失性存储器。

公开(公告)号：US20030090936A1

公开(公告)日：2003-05-15

申请号：US10277183

申请日：2002-10-21

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G11C016/04

CPC classification number: G11C16/20

Abstract: An electrically erasable and programmable memory (EEPROM) includes a memory array containing memory cells connected to word lines arranged in rows and to bit lines arranged in columns. The memory array includes a first special zone for storing special bits of a first type, and a second special zone for storing special bits of a second type. The first special zone includes a first row of memory cells connected to a first word line, wherein N1 memory cells are connected to N1 bit lines of a determined column of the memory array. The second special zone includes a second row of memory cells connected to a second word line, wherein N2 memory cells are connected to N2 other bit lines of the determined column. The N1 bit lines are not connected to the second row of memory cells, and the N2 bit lines are not connected to the first row of memory cells.

Abstract translation: 电可擦除可编程存储器（EEPROM）包括存储器阵列，存储器阵列包含连接到排列成行的字线和以列排列的位线的存储器单元。 存储器阵列包括用于存储第一类型的特殊位的第一特殊区域和用于存储第二类型的特殊位的第二特殊区域。 第一特殊区域包括连接到第一字线的第一行存储器单元，其中N1个存储器单元连接到存储器阵列的确定列的N1位线。 第二特殊区域包括连接到第二字线的第二行存储单元，其中N2个存储单元连接到所确定列的N2个其它位线。 N1位线未连接到第二行存储单元，N2位线未连接到第一行存储单元。

公开(公告)号：US20030035329A1

公开(公告)日：2003-02-20

申请号：US10178796

申请日：2002-06-24

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet ,  Francesco La Rosa

IPC: G11C029/00

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/08

Abstract: An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

Abstract translation: 电可编程和可擦除存储器包括存储单元，其中每个存储单元包括浮栅晶体管和存取晶体管。 浮栅晶体管具有连接到存取晶体管的第一端。 存储器包括用于在擦除阶段期间分别施加第一信号的电路和在要擦除的存储器单元的控制栅极和浮置栅极晶体管的第二端子上的第二信号。 该电路还适用于存储器单元的相应存取晶体管的栅极，以被擦除具有与第一信号的电压不同的电压的信号，并且相对于第二个电压的电压具有低或零电位差 信号。 保护存储器不受存取晶体管栅极氧化物击穿的影响。

公开(公告)号：US20020070757A1

公开(公告)日：2002-06-13

申请号：US09935292

申请日：2001-08-22

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: H03K019/0175

CPC classification number: G11C7/225 ,  G11C7/22 ,  H03K19/00361

Abstract: A buffer circuit includes an input for receiving a logic signal, and a transfer circuit for transferring the logic signal from the input to an output of the buffer circuit. The transfer circuit includes at least one logic gate having a trip point sensitive to a supply voltage of the buffer circuit. The buffer circuit further includes a delivery circuit for delivering an inhibit signal having a predetermined duration when the logic signal has a trailing edge and/or leading edge, and an inhibit circuit for inhibiting the transfer circuit and for isolating the output of the buffer circuit from the input of the buffer circuit when the inhibit signal is delivered. A storage circuit holds a logic value of the logic signal at the output of the buffer circuit when the inhibit signal is delivered.

Abstract translation: 缓冲电路包括用于接收逻辑信号的输入端和用于将逻辑信号从输入传送到缓冲电路的输出的传送电路。 传输电路包括至少一个具有对缓冲电路的电源电压敏感的跳变点的逻辑门。 缓冲电路还包括传送电路，用于在逻辑信号具有后沿和/或前沿时传送具有预定持续时间的禁止信号;以及禁止电路，用于禁止传输电路并将缓冲电路的输出与 当禁止信号被传送时缓冲电路的输入。 当禁止信号被传送时，存储电路保持在缓冲电路的输出处的逻辑信号的逻辑值。