公开(公告)号：US20020079545A1

公开(公告)日：2002-06-27

申请号：US09996071

申请日：2001-11-28

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray ,  Sigrid Thomas

IPC: H01L029/74

CPC classification number: H03K19/00315 ,  G11C5/145 ,  G11C8/08 ,  G11C16/0441 ,  G11C16/30

Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

Abstract translation: 高压开关装置包括用于将高电压切换到输出线并用于提供控制信号的开关电路。 高压开关装置还包括连接到开关电路的开关晶体管，用于基于控制信号将低电压切换到输出线。 输出信号由控制电路控制，该控制电路在开关晶体管的栅极电压电平的下降与由开关电路控制的输出线的电压电平之间建立控制回路。

公开(公告)号：US20020186599A1

公开(公告)日：2002-12-12

申请号：US10139621

申请日：2002-05-06

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

IPC: G11C007/00

CPC classification number: G11C16/0416

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract translation: 具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。 该选择晶体管用于由存储器单元的源选择单词。 以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。 独立于该选择，高电压切换到存储器单元的栅极和漏极。 这使得能够减少所需数量的高压开关。

公开(公告)号：US20020176298A1

公开(公告)日：2002-11-28

申请号：US10117448

申请日：2002-04-05

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas ,  Leila Aitouarab

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/26

Abstract: In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.

Abstract translation: 在用于读取存储器单元的装置中，预充电电路连接到要读取的存储器单元和与要读取的存储器单元相关联的参考单元。 预充电电路将差分放大器的输出预充电到预定的电压电平。 读取装置还包括连接到差分放大器的输出的具有高阈值和低阈值的反相器。 预定的电压电平对应于高和低阈值之间的中间电平。

公开(公告)号：US20030053349A1

公开(公告)日：2003-03-20

申请号：US10233052

申请日：2002-08-30

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas

IPC: G11C007/00

CPC classification number: G11C17/18

Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

Abstract translation: 存储器件包括以矩阵形式排列的多个存储单元。 每个存储单元包括串联连接的晶体管和电容器。 每个存储单元链接到连接列的存储单元的位线。 每个存储单元也链接到字线和第三行。 存储器单元的晶体管的栅极连接到字线，每个字线被连接到相应列中的晶体管的栅极。 第三条线连接到一行存储器单元的晶体管的源极。 位线连接到列的晶体管的电容器。 因此，可以通过字列和第三行来控制晶体管的栅极和源极之间的电压。

公开(公告)号：US20020191432A1

公开(公告)日：2002-12-19

申请号：US10172179

申请日：2002-06-14

Applicant: STMicroelectronics S.A.

Inventor： Sigrid Thomas

IPC: G11C005/06

CPC classification number: H01L27/11233 ,  G11C17/12 ,  H01L27/112

Abstract: A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.

Abstract translation: 由单元形成的只读存储器，每个单元在选择线和位线之间包括存储元件和选择MOS晶体管的串联连接，栅极连接到读控制线。 空白单元的存储元件是P沟道MOS晶体管，并且编程单元的存储元件是均匀的N型掺杂半导体区域。