公开(公告)号：US20140084397A1

公开(公告)日：2014-03-27

申请号：US14030867

申请日：2013-09-18

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni Ziglioli

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B7/007 ,  B81B2207/012 ,  B81B2207/096 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00014

Abstract: A wafer-level package for a MEMS integrated device, envisages: a first body integrating a micromechanical structure; a second body having an active region integrating an electronic circuit, coupled to the micromechanical structure; and a third body defining a covering structure for the first body. The second body defines a base portion of the package and has an inner surface coupled to which is the first body, and an outer surface provided on which are electrical contacts towards the electronic circuit; a routing layer has an inner surface set in contact with the outer surface of the second body and an outer surface that carries electrical contact elements towards the external environment. The third body defines a covering portion for covering the package and is directly coupled to the second body for closing a housing space for the first body.

Abstract translation: 用于MEMS集成器件的晶片级封装设想：集成微机械结构的第一体; 具有集成电子电路的有源区域的第二主体，耦合到所述微机械结构; 以及限定第一主体的覆盖结构的第三主体。 所述第二主体限定所述包装的基部，并且具有联接到所述第一主体的内表面，并且设置在所述外表面上的电接触朝向所述电子电路的外表面; 路由层具有与第二主体的外表面接触的内表面和将电接触元件朝外部环境承载的外表面。 第三主体限定用于覆盖封装的覆盖部分，并且直接联接到第二主体以封闭用于第一主体的容纳空间。

公开(公告)号：US20150035091A1

公开(公告)日：2015-02-05

申请号：US14341458

申请日：2014-07-25

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni Ziglioli

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0257 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3142 ,  H01L24/97 ,  H01L25/50 ,  H01L2924/181 ,  H04R19/005 ,  H01L2924/00012

Abstract: In order to manufacture a packaged device, a die having a sensitive region is bonded to a support, and a packaging mass of moldable material is molded on the support so as to surround the die. During molding of the packaging mass, a chamber is formed, which faces the sensitive region and is connected to the outside environment. To this end, a sacrificial mass of material that may evaporate/sublimate is dispensed on the sensitive region; the packaging mass is molded on the sacrificial mass; a through hole is formed in the packaging mass to extend as far as the sacrificial mass; the sacrificial mass is evaporated/sublimated through the hole.

Abstract translation: 为了制造包装的装置，将具有敏感区域的模具接合到支撑体上，并且将可模制材料的包装物质模制在支撑件上以包围模具。 在包装物料的成型期间，形成面对敏感区域并连接到外部环境的室。 为此，可以在敏感区域上分配可蒸发/升华的材料的牺牲物质; 包装质量被模制在牺牲块上; 在包装物质中形成一个通孔以延伸至牺牲块; 牺牲物质通过孔蒸发/升华。

公开(公告)号：US20180122752A1

公开(公告)日：2018-05-03

申请号：US15854456

申请日：2017-12-26

Applicant: STMicroelectronics S.r.I.

Inventor： Alberto Pagani ,  Giovanni Girlando ,  Federico Giovanni Ziglioli ,  Alessandro Finocchiaro

IPC: H01L23/00 ,  H01L23/58 ,  G01R31/28 ,  H01L21/66

CPC classification number: H01L23/562 ,  G01R31/2872 ,  H01L21/76224 ,  H01L22/14 ,  H01L23/585 ,  H01L2924/0002 ,  H02J50/20 ,  H01L2924/00

Abstract: A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.

公开(公告)号：US09011776B2

公开(公告)日：2015-04-21

申请号：US14013730

申请日：2013-08-29

Applicant: STMicroelectronics S.r.I.

Inventor： Federico Giovanni Ziglioli ,  Fulvio Vittorio Fontana ,  Luca Maggi

IPC: B81C1/00 ,  B81B7/00 ,  H04R19/04

CPC classification number: B81B7/0077 ,  B81B7/0058 ,  B81B2201/0264 ,  B81C1/00333 ,  B81C2203/0118 ,  H01L2224/48091 ,  H01L2224/48145 ,  H04R1/086 ,  H04R19/04 ,  H04R2201/003 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids.

Abstract translation: 一种封装器件，其中芯片的至少一个敏感部分被封装在由封装形成的腔室中。 该包装具有透气区域，具有多个孔和拒水结构，以使得能够在外部环境和室之间通过空气并阻止液体的通过。