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公开(公告)号：US20130320957A1
公开(公告)日：2013-12-05
申请号：US13764071
申请日：2013-02-11
Applicant: STMICROELECTRONICS S.R.L.
Inventor： SANTICARLO ADAMO , Sergio Fabiano , Francesco Pirozzi
IPC: G05F3/08
CPC classification number: G05F3/08 , G06F1/266 , G06F1/3296 , H02M3/157 , H02M2001/0025 , Y02D10/172
Abstract: A DC-DC converter includes an interface to receive data having voltage values. A first circuit carries out a voltage transition from a previously received voltage value to a received voltage value (VSEL). A second circuit activates or inactivates the first circuit in response to an activation signal or a stop signal provided by the interface. A third circuit configures the second circuit so that, when new data including a new voltage value is received during a voltage transition, the second circuit interprets the stop signal as an activation signal for the first circuit to carry out a new voltage transition. The setting circuit sets at least one parameter needed by the first circuit to carry out the new voltage transition in response to the new data and before the end of the new voltage transition.
Abstract translation: DC-DC转换器包括用于接收具有电压值的数据的接口。 第一电路执行从先前接收到的电压值到接收电压值（VSEL）的电压转变。 响应于由接口提供的激活信号或停止信号，第二电路激活或停用第一电路。 第三电路配置第二电路，使得当在电压转换期间接收到包括新电压值的新数据时，第二电路将停止信号解释为第一电路的激活信号，以执行新的电压转换。 设置电路设置第一电路所需的至少一个参数，以响应于新数据并在新的电压转换结束之前执行新的电压转换。
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公开(公告)号：US11831317B2
公开(公告)日：2023-11-28
申请号：US18064631
申请日：2022-12-12
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi , Santi Carlo Adamo
Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.
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公开(公告)号：US10303201B2
公开(公告)日：2019-05-28
申请号：US15478638
申请日：2017-04-04
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi
Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
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公开(公告)号：US20170207771A1
公开(公告)日：2017-07-20
申请号：US15478638
申请日：2017-04-04
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi
IPC: H03H17/02
CPC classification number: G06F1/08 , G06F15/76 , H03H17/0292 , H03H2220/04
Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
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公开(公告)号：US20160011625A1
公开(公告)日：2016-01-14
申请号：US14730408
申请日：2015-06-04
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi
CPC classification number: G06F1/08 , G06F15/76 , H03H17/0292 , H03H2220/04
Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
Abstract translation: 具有流水线结构的数字滤波器包括由各个时钟信号定时的处理结构。 每个处理结构又由用于处理输入样本的多个处理模块形成。 相位发生器使处理模块与输入样本对齐，使得每个输入样本由相应的一个处理模块处理。 当处理结构在不同的时钟频率（因此实现不同的时钟域）时操作时，使用上采样缓冲器和下采样缓冲器，以便在时钟域之间转换信号样本，以便在处理结构中进行处理。
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Patent Agency Ranking
公开(公告)号：US11552621B2
公开(公告)日：2023-01-10
申请号：US17539966
申请日：2021-12-01
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi , Santi Carlo Adamo
Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.
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公开(公告)号：US20220200584A1
公开(公告)日：2022-06-23
申请号：US17539966
申请日：2021-12-01
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi , Santi Carlo Adamo
Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.
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8.发明授权公开(公告)号：US09735599B2
公开(公告)日：2017-08-15
申请号：US14725506
申请日：2015-05-29
Applicant: STMicroelectronics S.r.l.
Inventor： Agatino Antonino Alessandro , Carmelo Alberto Santagati , Liliana Arcidiacono , Francesco Pirozzi
CPC classification number: H02J7/0052 , G01R31/3655 , H01M10/44
Abstract: A battery charger includes an input supply terminal configured to receive a supply signal and a battery terminal configured to be connected to a battery. A supply switching circuit is arranged between the battery terminal and the input supply terminal. A control device generates a control signal to control operation of the supply switching circuit. A fuel gauge device provide a digital estimation of a voltage signal across the battery. A correction device modifies the control signal in response to the digital estimation of the voltage signal across the battery if that digital estimation is outside of a value range between two thresholds.
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公开(公告)号：US09671819B2
公开(公告)日：2017-06-06
申请号：US14730408
申请日：2015-06-04
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi
CPC classification number: G06F1/08 , G06F15/76 , H03H17/0292 , H03H2220/04
Abstract: A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
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公开(公告)号：US08935548B2
公开(公告)日：2015-01-13
申请号：US13764071
申请日：2013-02-11
Applicant: STMicroelectronics S.R.L.
Inventor： Santicarlo Adamo , Sergio Fabiano , Francesco Pirozzi
CPC classification number: G05F3/08 , G06F1/266 , G06F1/3296 , H02M3/157 , H02M2001/0025 , Y02D10/172
Abstract: A DC-DC converter includes an interface to receive data having voltage values. A first circuit carries out a voltage transition from a previously received voltage value to a received voltage value (VSEL). A second circuit activates or inactivates the first circuit in response to an activation signal or a stop signal provided by the interface. A third circuit configures the second circuit so that, when new data including a new voltage value is received during a voltage transition, the second circuit interprets the stop signal as an activation signal for the first circuit to carry out a new voltage transition. The setting circuit sets at least one parameter needed by the first circuit to carry out the new voltage transition in response to the new data and before the end of the new voltage transition.
Abstract translation: DC-DC转换器包括用于接收具有电压值的数据的接口。 第一电路执行从先前接收到的电压值到接收电压值（VSEL）的电压转变。 响应于由接口提供的激活信号或停止信号，第二电路激活或停用第一电路。 第三电路配置第二电路，使得当在电压转换期间接收到包括新电压值的新数据时，第二电路将停止信号解释为第一电路的激活信号，以执行新的电压转换。 设置电路设置第一电路所需的至少一个参数，以响应于新数据并在新的电压转换结束之前执行新的电压转换。
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