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公开(公告)号：US20210367589A1
公开(公告)日：2021-11-25
申请号：US17393916
申请日：2021-08-04
Applicant: STMicroelectronics S.r.l.
Inventor： Liliana Arcidiacono , Santi Carlo Adamo
IPC: H03K5/15
Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.
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公开(公告)号：US10674578B1
公开(公告)日：2020-06-02
申请号：US16584059
申请日：2019-09-26
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Cala′ , Salvatore Pantano , Santi Carlo Adamo
Abstract: A circuit includes: a communication interface configured to receive data; a plurality of output terminals; a bank of input registers coupled to the communication interface; a bank of buffer registers; a bank of output registers; a signal generator configured to generate a plurality of output signals based on respective registers of the bank of output registers at respective output terminals; and a conversion stage configured to: when data is received by the bank of input registers from the communication interface, sequentially convert content of the input registers of the bank of input registers and store the converted content into corresponding buffer registers of the bank of buffer registers based on a conversion function, and when the conversion stage finishes storing the converted content into the buffer registers, simultaneously copy content from the buffer registers into corresponding output registers of the bank of output registers.
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公开(公告)号：US11831317B2
公开(公告)日：2023-11-28
申请号：US18064631
申请日：2022-12-12
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pirozzi , Santi Carlo Adamo
Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.
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公开(公告)号：US11431330B2
公开(公告)日：2022-08-30
申请号：US17393916
申请日：2021-08-04
Applicant: STMicroelectronics S.r.l.
Inventor： Liliana Arcidiacono , Santi Carlo Adamo
Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.
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公开(公告)号：US10757779B2
公开(公告)日：2020-08-25
申请号：US16273661
申请日：2019-02-12
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Cala′ , Santi Carlo Adamo
Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.
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Patent Agency Ranking
公开(公告)号：US09184606B2
公开(公告)日：2015-11-10
申请号：US13774324
申请日：2013-02-22
Applicant: STMicroelectronics S.r.l.
CPC classification number: H02J7/0029 , H02J7/0009 , H02J7/0022 , H02J7/0024 , H02J7/0031 , H02J7/0052 , H02J7/0068 , H02J7/0077 , H02J7/008 , H02J9/06 , H02J2007/0062
Abstract: A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.
Abstract translation: 一种电池充电器，包括被配置为接收电源信号的输入电源端子，被配置为连接到电池的电池端子，至少一个输出端子和电池端子与输出端子之间的电路径，至少一个装置， 检测电池或电池充电器的一个报警状态。 电池充电器包括被配置为当电池提供至少一个输出端子的定时间隔使能至少一个检测装置的电路。
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公开(公告)号：US20210111712A1
公开(公告)日：2021-04-15
申请号：US17035074
申请日：2020-09-28
Applicant: STMicroelectronics S.r.l.
Inventor： Liliana Arcidiacono , Santi Carlo Adamo
IPC: H03K5/15
Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.
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公开(公告)号：US10206258B2
公开(公告)日：2019-02-12
申请号：US15975059
申请日：2018-05-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Cala' , Santi Carlo Adamo
Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.
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公开(公告)号：US20180368227A1
公开(公告)日：2018-12-20
申请号：US15975059
申请日：2018-05-09
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Cala' , Santi Carlo Adamo
CPC classification number: H05B33/0845 , H03K3/017 , H03K7/08 , H05B33/0815
Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.
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公开(公告)号：US11271555B2
公开(公告)日：2022-03-08
申请号：US16995190
申请日：2020-08-17
Applicant: STMicroelectronics S.r.l.
Inventor： Ignazio Cala' , Santi Carlo Adamo
Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.
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