公开(公告)号：US20140310439A1

公开(公告)日：2014-10-16

申请号：US14027267

申请日：2013-09-16

申请人： Saeed Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

发明人： Saeed Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

摘要： A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold.

摘要翻译： 一种用于产生中断请求的方法，所述方法包括：由第一电路接收中断触发事件的发生的指示; 确定中断触发事件的发生与发生中断触发事件之前的最后一个中断触发事件的发生是否超过阈值; 如果所述时间差超过所述阈值，则由所述第一电路产生响应于所述中断触发事件的发生的中断请求; 并且在产生最后一个中断请求之后的预定延迟时间内延迟响应中断触发事件发生的中断请求的产生，如果时间差小于阈值。

公开(公告)号：US09697149B2

公开(公告)日：2017-07-04

申请号：US14027267

申请日：2013-09-16

申请人： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

发明人： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

IPC分类号： G06F13/24 ,  G06F3/06 ,  G06F9/48

CPC分类号： G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

摘要： A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold.

公开(公告)号：US20150120855A1

公开(公告)日：2015-04-30

申请号：US14066798

申请日：2013-10-30

申请人： Erez Izenberg ,  Leah Shalev ,  Zorik Machulsky ,  Nafea Bshara

发明人： Erez Izenberg ,  Leah Shalev ,  Zorik Machulsky ,  Nafea Bshara

IPC分类号： H04L29/08

CPC分类号： G06F15/17331 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/067 ,  H04L67/1097

摘要： A method for hybrid RDMA, the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing or indirectly writing in response to the determination.

摘要翻译： 一种用于混合RDMA的方法，所述方法可以包括：（i）由第一计算机接收通过网络从第二计算机发送的分组; 其中所述分组可以包括数据和元数据; （ii）响应于元数据确定数据是否应当（a）由第一计算机的第一硬件加速器直接写入第一计算机的第一应用存储器; 或（b）间接写入第一个应用程序内存; （iii）间接书面或间接写作以回应决定。

公开(公告)号：US20150169613A1

公开(公告)日：2015-06-18

申请号：US14108458

申请日：2013-12-17

申请人： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Zorik Machulsky ,  Ron Diamant

发明人： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Zorik Machulsky ,  Ron Diamant

IPC分类号： G06F17/30

CPC分类号： G06F17/30159 ,  G06F17/30283 ,  G06F17/30949

摘要： A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.

摘要翻译： 一种用于带内重复数据删除的方法，所述方法可以包括由硬件加速器接收传达第一数据块的第一分组序列的接收分组; 对接收到的分组应用数据块哈希计算处理，同时考虑在对接收到的分组之前的第一序列的最后分组应用数据块哈希计算处理时获得的哈希计算结果; 其中所述第一数据块哈希值的计算在所述硬件加速器完成所述第一数据块的整体完成之前启动。

公开(公告)号：US09141546B2

公开(公告)日：2015-09-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。

公开(公告)号：US20120127818A1

公开(公告)日：2012-05-24

申请号：US13302837

申请日：2011-11-22

申请人： Gil Levy ,  Nafea Bshara ,  Yaron Zimerman ,  Carmi Arad

发明人： Gil Levy ,  Nafea Bshara ,  Yaron Zimerman ,  Carmi Arad

IPC分类号： G11C8/00

CPC分类号： G06F13/16

摘要： In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory operation is performed using the content data stored in the first memory bank, and a second memory operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data.

摘要翻译： 在具有一组用于存储内容数据的存储器组的存储器件中，在单个时钟周期期间接收至少两个在第一存储体中执行相应存储器操作的请求。 所述至少两个请求中的一个或多个被阻止访问第一存储体，并且作为响应：访问与第一存储体相关联并且不同于存储在其中的内容数据的冗余数据，并且在不访问第一存储体的情况下，处于 基于相关联的冗余数据重建存储在第一存储体中的内容数据的至少一部分。 使用存储在第一存储体中的内容数据执行第一存储器操作，并且使用重构的内容数据i）执行第二存储器操作，而不访问第一存储体，以及ii）基于相关联的冗余数据。

公开(公告)号：US07796594B2

公开(公告)日：2010-09-14

申请号：US12030822

申请日：2008-02-13

申请人： David Melman ,  Nir Arad ,  Nafea Bshara

发明人： David Melman ,  Nir Arad ,  Nafea Bshara

IPC分类号： H04L12/28

CPC分类号： H04L45/04 ,  H04L12/46 ,  H04L12/4625 ,  H04L45/00 ,  H04L45/08 ,  H04L45/60 ,  H04L49/109 ,  H04L49/351

摘要： A system and method of extending a standard bridge to enable execution of logical bridging functionality are disclosed. In some implementations, a logical bridge may assign source logical port information to a data packet based on characteristics of the data packet, employ the source logical port information to learn the source address and to forward the data packet to a logical egress port, and map the logical egress port to a physical egress port at which the data packet is to be egressed. A tunnel interface may optionally be applied to a data packet upon egress.

摘要翻译： 公开了一种扩展标准网桥以实现逻辑桥接功能的执行的系统和方法。 在一些实现中，逻辑桥可以基于数据分组的特性将源逻辑端口信息分配给数据分组，使用源逻辑端口信息来学习源地址并将数据分组转发到逻辑出口端口，并且映射 到出口数据包的物理出口端口的逻辑出口端口。 隧道接口可以可选地在出口时应用于数据分组。

公开(公告)号：US08514651B2

公开(公告)日：2013-08-20

申请号：US13302837

申请日：2011-11-22

申请人： Gil Levy ,  Nafea Bshara ,  Yaron Zimerman ,  Carmi Arad

发明人： Gil Levy ,  Nafea Bshara ,  Yaron Zimerman ,  Carmi Arad

IPC分类号： G11C8/00

CPC分类号： G06F13/16

摘要： In a memory device having a set of memory banks to store content data, at least two requests to perform respective memory operations in a first memory bank are received during a single clock cycle. One or more of the at least two requests is blocked from accessing the first memory bank, and in response: redundancy data associated with the first memory bank and different from content data stored therein is accessed, and, without accessing the first memory bank, at least a portion of the content data stored in the first memory bank is reconstructed based on the associated redundancy data. A first memory operation is performed using the content data stored in the first memory bank, and a second memory operation is performed using content data reconstructed i) without accessing the first memory bank and ii) based on the associated redundancy data.

摘要翻译： 在具有一组用于存储内容数据的存储器组的存储器件中，在单个时钟周期期间接收至少两个在第一存储体中执行相应存储器操作的请求。 所述至少两个请求中的一个或多个被阻止访问第一存储体，并且作为响应：访问与第一存储体相关联并且不同于存储在其中的内容数据的冗余数据，并且在不访问第一存储体的情况下，处于 基于相关联的冗余数据重建存储在第一存储体中的内容数据的至少一部分。 使用存储在第一存储体中的内容数据执行第一存储器操作，并且使用重构的内容数据i）执行第二存储器操作，而不访问第一存储体，以及ii）基于相关联的冗余数据。

公开(公告)号：US08873428B1

公开(公告)日：2014-10-28

申请号：US13528436

申请日：2012-06-20

申请人： Michael Orr ,  Nafea Bshara

发明人： Michael Orr ,  Nafea Bshara

IPC分类号： H04L12/28

CPC分类号： H04L41/0893 ,  H04L41/082 ,  H04L63/0428 ,  H04L63/104

摘要： Embodiments provide a method for discovering, by a network device of a network, a plurality of network devices of the network; establishing, by the network device, a group of network devices, wherein the group of network devices comprises the network device and a subset of the plurality of network devices; receiving, by the network device, information that is pertinent to one or more network devices included in the group of network devices; processing the information to generate processed information; and propagating the processed information to one or more network devices of the subset of the plurality of network devices.

摘要翻译： 实施例提供了一种通过网络的网络设备发现网络的多个网络设备的方法; 由所述网络设备建立一组网络设备，其中所述一组网络设备包括所述网络设备和所述多个网络设备的子集; 由所述网络设备接收与所述网络设备组中包括的一个或多个网络设备相关的信息; 处理信息以生成处理信息; 以及将处理的信息传播到多个网络设备的子集的一个或多个网络设备。

公开(公告)号：US20140143487A1

公开(公告)日：2014-05-22

申请号：US13682781

申请日：2012-11-21

申请人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

发明人： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC分类号： G06F12/08

CPC分类号： G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

摘要： A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

摘要翻译： 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。