公开(公告)号：US06323126B1

公开(公告)日：2001-11-27

申请号：US08329806

申请日：1994-10-26

申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda

发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda

IPC分类号： H01L214763

CPC分类号： C23C16/0281 ,  C23C16/045 ,  C23C16/14 ,  H01L21/32051

摘要： A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF6, thereby forming a tungsten plug.

摘要翻译： 公开了形成钨丝塞和层的方法。 在接触开口内形成薄层的多晶硅或非晶硅。 硅暴露于WF6，由此形成钨丝塞。

公开(公告)号：US06500729B1

公开(公告)日：2002-12-31

申请号：US09586384

申请日：2000-06-02

申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.

摘要翻译： 形成浅沟槽隔离结构的方法产生具有基本平坦的上表面的浅沟槽隔离结构。 浅沟槽隔离结构由原始形成的浅沟槽隔离结构形成，其包括在沟槽内的沉积的介电材料，并且其呈现出形成在沟槽内的空隙形式的凹陷相关问题，其中沉积的介电材料的表面是 凹进平面上表面下方。 该方法提供用硅膜填充空隙。 然后以其沉积或氧化形式抛光硅膜，以产生具有平坦上表面的浅沟槽隔离结构。

公开(公告)号：US06358785B1

公开(公告)日：2002-03-19

申请号：US09588058

申请日：2000-06-06

申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

IPC分类号： H01L21338

CPC分类号： H01L21/76227

摘要： A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

摘要翻译： 在半导体衬底内形成浅沟槽隔离结构的方法包括在半导体衬底内形成具有抗氧化材料作为顶表面的沟槽开口。 氧化物衬垫形成在沟槽开口的内表面上。 然后将硅材料引入沟槽开口并在顶表面上。 在抛光操作用于平面化结构之前或之后，硅材料随后被氧化。 由于硅或氧化硅材料的抛光速率与耐氧化材料相似，并且小于常规形成的CVD氧化物的抛光速率，所以在抛光过程中避免了相关的问题。

公开(公告)号：US06325709B1

公开(公告)日：2001-12-04

申请号：US09442495

申请日：1999-11-18

申请人： Arun Kumar Nanda ,  Ser Wee Quek

发明人： Arun Kumar Nanda ,  Ser Wee Quek

IPC分类号： B24B2118

CPC分类号： B24B53/017 ,  B24B53/12 ,  B24D3/06 ,  B24D7/02 ,  B24D18/0018

摘要： A polishing pad conditioner used in the removal of slurry and semiconductor thin film build-up in the polishing pad in a chemical and mechanical polishing (CMP) process used to planarize a semiconductor wafer surface. The conditioner is pressed against the polishing pad, often while de-ionized water is applied, to remove the material build-up. The conditioner of the present invention has a convex lower surface covered by diamond crystals that are bonded to the underside of the nickel alloy conditioner. Typically, the difference between the center and the edge of the conditioning surface will range from a minimum of about 0.2 mm (very slightly convex) to a maximum of the entire thickness of the conditioning surface (more convex). The convex shape reduces the friction between the pad and conditioner and allows the slurry to reach the center of the conditioner. This more uniformly conditions the pad surface which yields more uniformly polished wafers and also increases pad life. Brazing is used to form a molecular bond between the abrasive diamond crystals and the nickel alloy conditioner. This bond is not attacked by the low pH slurry used in CMP, eliminating the problem where diamond crystals separate from the conditioner causing scratches on the wafer surface.

摘要翻译： 用于在用于平坦化半导体晶片表面的化学和机械抛光（CMP）工艺中用于去除抛光垫中的浆料和半导体薄膜积聚的抛光垫调节器。 调理剂经常在去离子水被施加时压在抛光垫上，以去除材料堆积。 本发明的护发素具有被金属晶体覆盖的凸下表面，其结合到镍合金调理剂的下侧。 通常，调理表面的中心和边缘之间的差异将在调节表面的整个厚度的最小值（更凸）的范围内为最小约0.2mm（非常微凸）。 凸形减小垫和调节剂之间的摩擦，并允许浆料到达护发素的中心。 这更均匀地调节焊盘表面，产生更均匀的抛光晶片，并且还增加焊盘寿命。 钎焊用于在磨料金刚石晶体和镍合金调节剂之间形成分子键。 这种键不受CMP中使用的低pH浆料的侵害，消除了金刚石晶体与调理剂分离而造成晶片表面划痕的问题。

公开(公告)号：US6110012A

公开(公告)日：2000-08-29

申请号：US220417

申请日：1998-12-24

申请人： Alvaro Maury ,  Arun Kumar Nanda ,  Jose Omar Rodriguez

发明人： Alvaro Maury ,  Arun Kumar Nanda ,  Jose Omar Rodriguez

IPC分类号： H01L21/302 ,  B24B37/32 ,  B24B57/02 ,  H01L21/304 ,  B24B1/00 ,  B24B29/00

CPC分类号： B24B37/32 ,  B24B57/02

摘要： A method and apparatus for limiting or eliminating the edge effect in a chemical mechanical polishing apparatus comprising a substrate holder and a retaining ring spaced from and around the holder, a rotatable platen and a polishing pad on the platen, by essentially flattening the pad in the area in which it normally tends to deform. The invention is carried out by applying a fluid under pressure, preferably the polishing slurry, to the pad in the region of the gap between the retaining ring and the holder to substantially flatten the pad in the area around the edge of the substrate.

摘要翻译： 一种用于限制或消除化学机械抛光装置中的边缘效应的方法和装置，其包括基板保持器和保持器间隔开并围绕保持器的可移动压板和抛光垫，通过使垫 其通常倾向于变形的区域。 本发明通过将压力下的流体（优选抛光浆料）施加到保持环和保持器之间的间隙区域中的垫上，以在基板边缘周围的区域中使焊盘基本上平坦化。

公开(公告)号：US5686359A

公开(公告)日：1997-11-11

申请号：US569025

申请日：1995-12-07

申请人： Steven Glenn Meester ,  Arun Kumar Nanda ,  Cletus Walter Wilkins

发明人： Steven Glenn Meester ,  Arun Kumar Nanda ,  Cletus Walter Wilkins

IPC分类号： H01L21/28 ,  H01L21/285

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  Y10S438/934

摘要： The specification describes a process for siliciding silicon metallization with titanium. The process requires two anneal steps and is based on careful control of operating parameters during the first anneal step. A prescription is given relating time and temperature of anneal, and titanium film thickness, to silicide resistivity. Proper choice of parameters also minimizes variables in the process.

摘要翻译： 本说明书描述了用钛硅化硅金属化的方法。 该过程需要两个退火步骤，并且基于在第一退火步骤期间对操作参数的仔细控制。 给出了退火时间和温度以及钛膜厚度与硅化物电阻率的处方。 参数的正确选择也使过程中的变量最小化。

公开(公告)号：US5641994A

公开(公告)日：1997-06-24

申请号：US668310

申请日：1996-06-26

申请人： Cheryl Anne Bollinger ,  Edward Alan Dein ,  Sailesh Mansinh Merchant ,  Arun Kumar Nanda ,  Pradip Kumar Roy ,  Cletus Walter Wilkins, Jr.

发明人： Cheryl Anne Bollinger ,  Edward Alan Dein ,  Sailesh Mansinh Merchant ,  Arun Kumar Nanda ,  Pradip Kumar Roy ,  Cletus Walter Wilkins, Jr.

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/482 ,  H01L23/532 ,  H01L27/04 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53223 ,  H01L23/4827 ,  H01L2224/04026 ,  H01L2924/01021 ,  H01L2924/10253

摘要： A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.

摘要翻译： Si IC包括Al基层，其被沉积为不同组成的Al基材料的亚层的复合物。 在一个实施例中，第一子层包括Al-Si基合金，其被设置为防止实质的Si迁移到第一子层中，并且第一子层在第一子层之上包括基本上不含Si的Al基合金以减轻沉淀 - 引起的问题。