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    Method for reducing dishing related issues during the formation of shallow trench isolation structures
    1.
    发明授权
    Method for reducing dishing related issues during the formation of shallow trench isolation structures 有权
    在形成浅沟槽隔离结构期间减少凹陷相关问题的方法

    公开(公告)号：US06500729B1

    公开(公告)日：2002-12-31

    申请号：US09586384

    申请日：2000-06-02

    申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

    发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.

    摘要翻译： 形成浅沟槽隔离结构的方法产生具有基本平坦的上表面的浅沟槽隔离结构。 浅沟槽隔离结构由原始形成的浅沟槽隔离结构形成，其包括在沟槽内的沉积的介电材料，并且其呈现出形成在沟槽内的空隙形式的凹陷相关问题，其中沉积的介电材料的表面是 凹进平面上表面下方。 该方法提供用硅膜填充空隙。 然后以其沉积或氧化形式抛光硅膜，以产生具有平坦上表面的浅沟槽隔离结构。

    Method for forming shallow trench isolation structures
    2.
    发明授权
    Method for forming shallow trench isolation structures 有权
    形成浅沟槽隔离结构的方法

    公开(公告)号：US06358785B1

    公开(公告)日：2002-03-19

    申请号：US09588058

    申请日：2000-06-06

    申请人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

    发明人： Sailesh Chittipeddi ,  Arun Kumar Nanda ,  Ankineedu Velaga

    IPC分类号： H01L21338

    CPC分类号： H01L21/76227

    摘要： A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

    摘要翻译： 在半导体衬底内形成浅沟槽隔离结构的方法包括在半导体衬底内形成具有抗氧化材料作为顶表面的沟槽开口。 氧化物衬垫形成在沟槽开口的内表面上。 然后将硅材料引入沟槽开口并在顶表面上。 在抛光操作用于平面化结构之前或之后，硅材料随后被氧化。 由于硅或氧化硅材料的抛光速率与耐氧化材料相似，并且小于常规形成的CVD氧化物的抛光速率，所以在抛光过程中避免了相关的问题。

    Silicide formation on polysilicon
    3.
    发明授权
    Silicide formation on polysilicon 失效
    多晶硅上的硅化物形成

    公开(公告)号：US5147820A

    公开(公告)日：1992-09-15

    申请号：US749762

    申请日：1991-08-26

    申请人： Sailesh Chittipeddi ,  Pradip K. Roy ,  Ankineedu Velaga

    发明人： Sailesh Chittipeddi ,  Pradip K. Roy ,  Ankineedu Velaga

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

    CPC分类号： H01L21/28052

    摘要： An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

    Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer
    7.
    发明授权
    Silicon-on-insulator (SOI) semiconductor structure with additional trench including a conductive layer 有权
    绝缘体上硅（SOI）半导体结构，具有包括导电层的附加沟槽

    公开(公告)号：US06538283B1

    公开(公告)日：2003-03-25

    申请号：US09611907

    申请日：2000-07-07

    申请人： Sailesh Chittipeddi ,  Michael J. Kelly

    发明人： Sailesh Chittipeddi ,  Michael J. Kelly

    IPC分类号： H01L2701

    CPC分类号： H01L29/66181 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/0805 ,  H01L27/1203

    摘要： A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, and a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the base substrate, the insulator layer and the silicon layer, wherein the at least one trench includes at least one layer of silicon dioxide formed therein. In a preferred embodiment, semiconductor material disposed in the at least one trench forms a first electrode of a semiconductor capacitor, and semiconductor material of the SOI substrate which lies adjacent to the at least one trench forms a second electrode of the capacitor.

    摘要翻译： 一种包括绝缘体上硅（SOI）衬底的半导体器件，包括基底衬底，绝缘体层和硅层，以及沟槽电容器，其包括形成在绝缘体上硅衬底中的至少一个沟槽， 基底衬底，绝缘体层和硅层，其中至少一个沟槽包括在其中形成的至少一层二氧化硅。 在优选实施例中，设置在至少一个沟槽中的半导体材料形成半导体电容器的第一电极，并且位于与至少一个沟槽相邻的SOI衬底的半导体材料形成电容器的第二电极。

    Transistor fabrication method
    8.
    发明授权
    Transistor fabrication method 失效
    晶体管制造方法

    公开(公告)号：US06498080B1

    公开(公告)日：2002-12-24

    申请号：US08587061

    申请日：1996-01-16

    申请人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    发明人： Sailesh Chittipeddi ,  Taeho Kook ,  Avinoam Kornblit

    IPC分类号： H01L213205

    CPC分类号： H01L29/66575 ,  H01L21/0276 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

    摘要翻译： 公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。 使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。 可以形成各种硅化和非硅化的结构。

    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers
    9.
    发明授权
    Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers 有权
    包括夹在氮化硅层之间的五氧化二钽层的半导体器件结构

    公开(公告)号：US06482694B2

    公开(公告)日：2002-11-19

    申请号：US09878657

    申请日：2001-06-11

    申请人： Sailesh Chittipeddi ,  Charles Walter Pearce

    发明人： Sailesh Chittipeddi ,  Charles Walter Pearce

    IPC分类号： H01L218242

    CPC分类号： H01L28/40 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185 ,  H01L27/0805 ,  H01L27/1085

    摘要： An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the SixNy/Ta2O5/SixNy structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the SixNy/Ta2O5/SixNy structure.

    摘要翻译： 绝缘结构包括第一氮化硅层，形成在第一氮化硅（SiNx）层上方的五氧化二钽层和形成在五氧化二钽（Ta2O5）上方的第二氮化硅层。 SiNx覆层在加热期间防止钽的扩散。 提供高介电常数。 绝缘结构的热稳定性提高。 绝缘结构可以包括在电容器或浅沟槽隔离结构中。 示例性电容器由基板，下电极，三层SixNy / Ta2O5 / SixNy结构和上电极形成。 下电极可以包括在铝层上形成的TiN层，或者形成在多晶硅层上的TiN层，或者在其上形成有氧化物阻挡层的多晶硅层。 上电极可以是TiN层或多晶硅层。 示例性的浅沟槽隔离结构包括作为衬底在衬底表面的浅沟槽的侧面和底部上的SixNy / Ta2O5 / SixNy结构。 浅沟槽中填充有氧化物，如TEOS。 可以使用各种方法来制造包括SixNy / Ta2O5 / SixNy结构的器件。