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    System and method for pseudo-random test pattern memory allocation for processor design verification and validation
    1.
    发明授权
    System and method for pseudo-random test pattern memory allocation for processor design verification and validation 失效
    用于处理器设计验证和验证的伪随机测试模式存储器分配的系统和方法

    公开(公告)号：US07584394B2

    公开(公告)日：2009-09-01

    申请号：US11779394

    申请日：2007-07-18

    申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/00

    CPC分类号： G06F11/263

    摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

    摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果进行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。

    System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation
    2.
    发明申请
    System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation 失效
    用于处理器设计验证和验证的伪随机测试模式存储器分配的系统和方法

    公开(公告)号：US20090024891A1

    公开(公告)日：2009-01-22

    申请号：US11779394

    申请日：2007-07-18

    申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/30

    CPC分类号： G06F11/263

    摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

    摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果执行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。

    System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation
    4.
    发明授权
    System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation 有权
    通过在多个测试模式进行处理器设计验证和验证后计算CRC计算来提高错误检查性能的系统和方法

    公开(公告)号：US07739570B2

    公开(公告)日：2010-06-15

    申请号：US11779385

    申请日：2007-07-18

    申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F11/261 ,  G06F11/263

    摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

    摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

    System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation
    6.
    发明申请
    System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation 有权
    通过计算处理器设计验证和验证的多个测试模式后的CRC计算来增加错误检查性能的系统和方法

    公开(公告)号：US20090024873A1

    公开(公告)日：2009-01-22

    申请号：US11779385

    申请日：2007-07-18

    申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    IPC分类号： G06F11/263

    CPC分类号： G06F11/261 ,  G06F11/263

    摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

    摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

    System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation
    7.
    发明授权
    System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation 失效
    用于预测处理器设计验证和验证的测试模式生成和仿真中的lwarx和stwcx指令的系统和方法

    公开(公告)号：US07689886B2

    公开(公告)日：2010-03-30

    申请号：US11779390

    申请日：2007-07-18

    申请人： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/00

    CPC分类号： G01R31/31813 ,  G01R31/318357 ,  G11C29/56

    摘要： A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution.

    摘要翻译： 提出了一种用于预测lwarx（Load Word And Reserve Index form）和stwcx（Store Word Conditional）指令结果的系统和方法。 lwarx指令在地址/粒子上建立一个预留，只有当粒子的预留仍然存在（条件存储）​​时，针对相同地址/粒子的stwcx指令才会成功“成功”。 由于可能由于诸如执行不同的lwarx或ldarx指令（或其他机制）的处理器（或另一个处理器）的情况而丢失预留，这清除了第一个预留并建立了新的预留，因此本文描述了本发明 以确保stwcx成功和失败可预测性的方式构建测试模式。 因此，stwcx指令在测试模式执行期间是可测试的。

    System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation
    8.
    发明申请
    System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation 有权
    使用测试模式重新执行的系统和方法在处理器设计验证和验证的不同时序方案中

    公开(公告)号：US20090024892A1

    公开(公告)日：2009-01-22

    申请号：US11779395

    申请日：2007-07-18

    申请人： Vinod Bussa ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil ,  Bhavani Shringari Nanjundiah

    发明人： Vinod Bussa ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/263

    CPC分类号： G06F11/261 ,  G06F11/263

    摘要： A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.

    摘要翻译： 介绍了使用测试模式重新执行的系统和方法处理器测试。 处理器使用不同的时序场景重新执行测试模式，以减少测试模式构建时间并提高系统测试覆盖率。 本文描述的本发明改变了当重新执行测试模式时处理器的存储器（高速缓存，TLB，SLB等）的初始状态，其进而改变了定时场景。 通过重新执行测试模式，而不是重建新的测试模式，验证质量得到改善，因为有更多的时间可用于执行，验证和验证。 此外，由于测试模式产生相同的最终状态，本文所述的发明也简化了错误检查。

    System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation
    10.
    发明申请
    System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation 失效
    用于预测处理器设计验证和验证的测试模式生成和仿真中的lwarx和stwcx指令的系统和方法

    公开(公告)号：US20090024886A1

    公开(公告)日：2009-01-22

    申请号：US11779390

    申请日：2007-07-18

    申请人： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Sampan Arora ,  Divya S. Anvekar ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G11C29/00

    CPC分类号： G01R31/31813 ,  G01R31/318357 ,  G11C29/56

    摘要： A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution.

    摘要翻译： 提出了一种用于预测lwarx（Load Word And Reserve Index form）和stwcx（Store Word Conditional）指令结果的系统和方法。 lwarx指令在地址/粒子上建立一个预留，只有当粒子的预留仍然存在（条件存储）​​时，针对相同地址/粒子的stwcx指令才会成功“成功”。 由于可能由于诸如执行不同的lwarx或ldarx指令（或其他机制）的处理器（或另一个处理器）的情况而丢失预留，这清除了第一个预留并建立了新的预留，因此本文描述了本发明 以确保stwcx成功和失败可预测性的方式构建测试模式。 因此，stwcx指令在测试模式执行期间是可测试的。