公开(公告)号：US07584394B2

公开(公告)日：2009-09-01

申请号：US11779394

申请日：2007-07-18

申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC分类号： G06F11/00

CPC分类号： G06F11/263

摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果进行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。

公开(公告)号：US20090024891A1

公开(公告)日：2009-01-22

申请号：US11779394

申请日：2007-07-18

申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

IPC分类号： G06F11/30

CPC分类号： G06F11/263

摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果执行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。

公开(公告)号：US07669083B2

公开(公告)日：2010-02-23

申请号：US11853130

申请日：2007-09-11

申请人： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

发明人： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G06F11/2236

摘要： A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

摘要翻译： 提出了一种通过混合测试用例指令顺序从一个测试用例创建多个测试用例场景的系统和方法，同时保持相对子测试用例指令顺序完整。 一个测试用例生成器生成并提供一个包含多个子测试用例的测试用例给测试用例执行器。 反过来，测试用例执行器递归地调度并将不同的混洗指令命令的测试用例调度到处理器，以便有效地测试处理器。 在一个实施例中，测试用例生成器向测试用例执行器提供多个测试用例。 在另一个实施例中，测试用例生成器向多个测试用例执行器提供测试用例，这些测试用例执行器又将洗牌测试用例并将洗牌的测试用例提供给它们各自的处理器。

公开(公告)号：US07739570B2

公开(公告)日：2010-06-15

申请号：US11779385

申请日：2007-07-18

申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/261 ,  G06F11/263

摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

公开(公告)号：US20090070631A1

公开(公告)日：2009-03-12

申请号：US11853130

申请日：2007-09-11

申请人： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

发明人： Sampan Arora ,  Sandip Bag ,  Vinod Bussa ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana ,  Shiraz Mohammad Zaman

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G06F11/2236

摘要： A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

摘要翻译： 提出了一种通过混合测试用例指令顺序从一个测试用例创建多个测试用例场景的系统和方法，同时保持相对子测试用例指令顺序完整。 一个测试用例生成器生成并提供一个包含多个子测试用例的测试用例给测试用例执行器。 反过来，测试用例执行器递归地调度并将不同的混洗指令命令的测试用例调度到处理器，以便有效地测试处理器。 在一个实施例中，测试用例生成器向测试用例执行器提供多个测试用例。 在另一个实施例中，测试用例生成器向多个测试用例执行器提供测试用例，这些测试用例执行器又将洗牌测试用例并将洗牌的测试用例提供给它们各自的处理器。

公开(公告)号：US20090024873A1

公开(公告)日：2009-01-22

申请号：US11779385

申请日：2007-07-18

申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

IPC分类号： G06F11/263

CPC分类号： G06F11/261 ,  G06F11/263

摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

公开(公告)号：US07752499B2

公开(公告)日：2010-07-06

申请号：US11853189

申请日：2007-09-11

申请人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

发明人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

IPC分类号： G06F11/00

CPC分类号： G06F11/263

摘要： A system and method for using resource pools and instruction pools for processor design verification and validation is presented. A test case generator organizes processor resources into resource pools using a resource pool mask. Next, the test case generator separates instructions into instruction pools based upon the resources that each instruction requires. The test case generator then creates a test case using one or more sub test cases by assigning a resource pool to each sub test case, identifying instruction pools that correspond the assigned test case, and building each sub test case using instructions included in the identified instruction pools.

摘要翻译： 介绍了一种使用资源池和指令池进行处理器设计验证和验证的系统和方法。 测试用例生成器使用资源池掩码将处理器资源组织到资源池中。 接下来，测试用例发生器根据每个指令需要的资源将指令分离为指令池。 然后，测试用例生成器使用一个或多个子测试用例，通过向每个子测试用例分配资源池来创建测试用例，识别与分配的测试用例对应的指令池，以及使用所述指令中包含的指令来构建每个子测试用例 游泳池。

公开(公告)号：US20090070570A1

公开(公告)日：2009-03-12

申请号：US11853208

申请日：2007-09-11

申请人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

发明人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

IPC分类号： G06F9/30 ,  G06F11/263

CPC分类号： G06F11/2236

摘要： A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt.

摘要翻译： 提出了一种用于将独立指令包含在测试用例中以有意引发可能与指令混洗过程结合使用的中断的系统和方法。 测试用例生成器构建测试用例，其包括有意中断指令，其被构造为有意地引起中断，例如指令存储中断（ISI），数据存储中断（DSI）和对齐中断和/或程序 中断（PI）。 当处理器执行测试用例并对中断处理程序调用中断时，中断处理程序不会解析中断，而是在指令之后的指令之后递增指令地址寄存器或链接寄存器并恢复测试用例执行 中断。

公开(公告)号：US20090024876A1

公开(公告)日：2009-01-22

申请号：US11779378

申请日：2007-07-18

申请人： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

发明人： Sampan Arora ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Chakrapani Rayadurgam

IPC分类号： G06F11/26

CPC分类号： G06F11/263 ,  G06F11/261

摘要： A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

摘要翻译： 提出了一种用于使用由分支指令创建的指令流“孔”来验证高速缓存监听逻辑和指令高速缓存与数据高速缓存之间的一致性的系统和方法。 测试模式生成器包括将数据加载/存储到指令流孔中的指令。 反过来，通过执行测试模式，处理器线程将L2高速缓存行加载到指令高速缓存（icache）和数据高速缓存（dcache）中。 测试模式根据存储指令修改dcache中的数据。 反过来，本文描述的发明识别窥探逻辑是否检测到改变并相应地更新icache的相应缓存行。

公开(公告)号：US08099559B2

公开(公告)日：2012-01-17

申请号：US11853201

申请日：2007-09-11

申请人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

发明人： Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F11/3684 ,  G06F11/2236 ,  G06F12/1027 ,  G06F2212/683

摘要： A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB.

摘要翻译： 提出了一种用于有意无效翻译条目有效位的系统和方法，以便在执行测试用例时引发存储中断。 在执行测试用例之前，中断处理器通过改变特定的有效位来伪随机地使包含在转换后备缓冲器（TLB）中的多个转换条目无效，以便引起诸如指令存储中断（ISI）的初始存储中断， 或数据存储中断（DSI）。 一旦处理器执行测试用例，反过来又触发存储中断，中断处理程序使用索引计数器来验证特定的有效位，并使其他有效位无效，从而引发后续的存储中断。 在一个实施例中，当处理器以除TLB之外的访问页表的模式执行时，中断处理程序也改变页表中的有效位。