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    Flexible display
    1.
    发明授权
    Flexible display 有权

    公开(公告)号：US10964770B2

    公开(公告)日：2021-03-30

    申请号：US16384340

    申请日：2019-04-15

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Gyungsoon Park ,  Minjae Jeong ,  Keumnam Kim ,  Sehyoung Cho ,  Jongho Hong

    IPC: H01L27/32 ,  H01L51/00 ,  G09G3/20

    Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

    Display apparatus
    2.
    发明授权
    Display apparatus 有权

    公开(公告)号：US10431606B2

    公开(公告)日：2019-10-01

    申请号：US15871103

    申请日：2018-01-15

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jangmi Kang ,  Meehye Jung ,  Hyunjoon Kim ,  Cheolgon Lee ,  Sehyoung Cho ,  Injae Hwang

    IPC: H01L27/12 ,  H01L23/00 ,  H01L27/32 ,  H01L29/786 ,  H01L51/05

    Abstract: A display device includes a substrate including a display region, and a peripheral region that is outside of the display region, a plurality of dummy pads at the peripheral region, an insulating layer covering the plurality of dummy pads, wherein top surfaces of first portions of the insulating layer above the plurality of dummy pads are higher than top surfaces of second portions of the insulating layer between the plurality of dummy pads, and a plurality of pads over the second portions of the insulating layer at the peripheral region.

    GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
    4.
    发明申请
    GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20170110076A1

    公开(公告)日：2017-04-20

    申请号：US15227924

    申请日：2016-08-03

    Applicant: Samsung Display Co., Ltd.

    Inventor： Junghwan Hwang ,  Sehyoung Cho

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2310/0286

    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

    Scan driver which reduces a voltage ripple
    7.
    发明授权
    Scan driver which reduces a voltage ripple 有权

    公开(公告)号：US09978328B2

    公开(公告)日：2018-05-22

    申请号：US15019741

    申请日：2016-02-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Sehyoung Cho ,  Kyunghoon Kim ,  Dongwoo Kim ,  Ilgon Kim ,  Kangmoon Jo ,  Hyunjoon Kim

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G2310/0286

    Abstract: There is provided a scan driver. The scan driver includes stages. An ith (i is a natural number) stage circuit includes an output unit, a controller configured to control the voltage of the second node in response to a kth (k is a natural number) clock signal supplied to a second input terminal, and an input unit configured to control the voltages of the first node and the second node in response to a carry signal of a previous stage that is supplied to a third input terminal and a carry signal of at least one next stage. The kth clock signal maintains a gate on voltage at a point of time at which a voltage of the jth clock signal is changed to a gate on voltage.

    Flexible display
    8.
    发明授权
    Flexible display 有权

    公开(公告)号：US10263062B2

    公开(公告)日：2019-04-16

    申请号：US14805765

    申请日：2015-07-22

    Applicant: Samsung Display Co., Ltd.

    Inventor： Gyungsoon Park ,  Minjae Jeong ,  Keumnam Kim ,  Sehyoung Cho ,  Jongho Hong

    IPC: H01L27/32 ,  H01L51/00 ,  G09G3/20

    Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

    Gate driving circuit and display apparatus including the same
    10.
    发明授权
    Gate driving circuit and display apparatus including the same 有权

    公开(公告)号：US09786243B2

    公开(公告)日：2017-10-10

    申请号：US14936434

    申请日：2015-11-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Sehyoung Cho ,  Kyung-hoon Kim ,  Dongwoo Kim ,  Ilgon Kim ,  Kangmoon Jo

    IPC: H03K17/687 ,  G09G3/36

    CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3696 ,  G09G2310/0251 ,  G09G2310/08

    Abstract: A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.

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