Gate driving circuit and display apparatus including the same

    公开(公告)号:US09786243B2

    公开(公告)日:2017-10-10

    申请号:US14936434

    申请日:2015-11-09

    IPC分类号: H03K17/687 G09G3/36

    摘要: A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.

    Display apparatus
    7.
    发明授权

    公开(公告)号:US11653542B2

    公开(公告)日:2023-05-16

    申请号:US17572922

    申请日:2022-01-11

    IPC分类号: H01L27/32 H01L51/00 H01L51/52

    摘要: A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench.

    DISPLAY APPARATUS
    8.
    发明申请
    DISPLAY APPARATUS 审中-公开

    公开(公告)号:US20190140044A1

    公开(公告)日:2019-05-09

    申请号:US16181283

    申请日:2018-11-05

    IPC分类号: H01L27/32 H01L51/52 H01L51/00

    摘要: A display apparatus includes a substrate; a plurality of display units on the substrate, each including a thin film transistor including at least one inorganic layer, a passivation layer on the thin film transistor, and a display device electrically connected to the thin film transistor; and a plurality of encapsulation layers respectively encapsulating the plurality of display units. The substrate includes a plurality of islands spaced apart, a plurality of connection units connecting the plurality of islands, and a plurality of through holes penetrating through the substrate between the plurality of connection units. The plurality of display units are on the plurality of islands, respectively. The at least one inorganic layer and the passivation layer extend on the plurality of connection units. The passivation layer includes a trench exposing the at least one inorganic layer. The encapsulation layer contacts the at least one inorganic layer exposed via the trench.

    Scan driver which reduces a voltage ripple

    公开(公告)号:US09978328B2

    公开(公告)日:2018-05-22

    申请号:US15019741

    申请日:2016-02-09

    IPC分类号: G09G3/36

    CPC分类号: G09G3/3677 G09G2310/0286

    摘要: There is provided a scan driver. The scan driver includes stages. An ith (i is a natural number) stage circuit includes an output unit, a controller configured to control the voltage of the second node in response to a kth (k is a natural number) clock signal supplied to a second input terminal, and an input unit configured to control the voltages of the first node and the second node in response to a carry signal of a previous stage that is supplied to a third input terminal and a carry signal of at least one next stage. The kth clock signal maintains a gate on voltage at a point of time at which a voltage of the jth clock signal is changed to a gate on voltage.