公开(公告)号：US20230215954A1

公开(公告)日：2023-07-06

申请号：US18176454

申请日：2023-02-28

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： YONG SU LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung Kim ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L29/78618 ,  H01L27/1288 ,  H01L27/124 ,  H01L29/7869 ,  H01L27/1225 ,  H01L29/78696 ,  H01L29/66969 ,  H01L29/41733 ,  H10K59/1213

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20150194534A1

公开(公告)日：2015-07-09

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US20240413248A1

公开(公告)日：2024-12-12

申请号：US18808905

申请日：2024-08-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H10K59/121

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20150279690A1

公开(公告)日：2015-10-01

申请号：US14735306

申请日：2015-06-10

Applicant: Samsung Display Co., Ltd.

Inventor： Yong-Hwan RYU ,  Dae Ho KIM ,  Hong Sick PARK ,  Shin Il CHOI

IPC: H01L21/311 ,  H01L21/308 ,  H01L27/12 ,  H01L21/321

CPC classification number: H01L21/31144 ,  H01L21/28 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76802 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/1288

Abstract: A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask.

Abstract translation: 一种形成薄膜晶体管阵列面板的方法包括：在衬底上形成第一绝缘层; 在所述第一绝缘层上形成无定形碳层; 在所述无定形碳层上形成第二绝缘层; 通过图案化所述第二绝缘层和所述无定形碳层在所述无定形碳层中形成开口; 以及通过蚀刻所述第一绝缘层在所述第一绝缘层中形成沟槽，使用包括所述开口的所述无定形碳层作为掩模来蚀刻所述第一绝缘层。