公开(公告)号：US20150044817A1

公开(公告)日：2015-02-12

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Wood Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/66 ,  H01L21/477 ,  H01L21/441 ,  H01L21/02 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US09455276B2

公开(公告)日：2016-09-27

申请号：US14456154

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Hee Jun Byeon ,  Seung Sok Son ,  Bo Sung Kim ,  Yeon Taek Jeong

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1343

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1259

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 栅极线和公共电压线，并且彼此电分离; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的第一钝化层; 在第一钝化层上的公共电极; 公共电极上的第二钝化层; 以及第二钝化层上的像素电极和连接构件，并且彼此电分离。 在第一钝化层和第二钝化层中限定第一接触孔和第二接触孔。 像素电极和漏极通过第二接触孔相互连接。 连接构件和公共电极通过第一接触孔彼此连接。

公开(公告)号：US09136342B2

公开(公告)日：2015-09-15

申请号：US14495835

申请日：2014-09-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract translation: 提供薄膜晶体管。 根据本发明的示例性实施例的薄膜晶体管包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 半导体层，设置在所述基板上，并且至少包括与所述栅电极重叠的部分; 设置在所述栅极线和所述半导体层之间的栅极绝缘层; 以及设置在所述基板上并且在所述半导体层的沟道区域上彼此面对的源电极和漏电极。 栅极绝缘层包括第一区域和第二区域，第一区域对应于半导体层的沟道区域，第一区域由第一材料制成，第二区域由第二材料制成，第一材料 并且第二材料具有不同的碳和硅原子数比。

公开(公告)号：US09406785B2

公开(公告)日：2016-08-02

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/441 ,  H01L21/02 ,  H01L21/385 ,  H01L29/66 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US09059112B1

公开(公告)日：2015-06-16

申请号：US14253040

申请日：2014-04-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yeon Taek Jeong ,  Hee Jun Byeon

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/12

CPC classification number: H01L27/1259 ,  H01L22/34 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/0031

Abstract: A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer.

Abstract translation: 显示装置包括：第一绝缘基板，包括显示区域，外围区域和测试区域;在第一绝缘基板上包括测试元件组栅电极，栅极电极和栅极线的栅极导体，栅绝缘层， 栅极导体，包括测试元件组半导体层和栅极绝缘层上的像素半导体层的半导体层，包括测试元件组源电极，测试元件组漏电极，包括源电极的数据线的数据导体 以及半导体层上的漏电极，数据导体上的第一钝化层，第一钝化层上的测试元件组公共电极和像素公共电极，测试元件组公共电极上的第二钝化层和像素 公共电极和第二钝化层上的像素电极。

公开(公告)号：US08895977B2

公开(公告)日：2014-11-25

申请号：US13673195

申请日：2012-11-09

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/786 ,  H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US20130320327A1

公开(公告)日：2013-12-05

申请号：US13673195

申请日：2012-11-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung LEE ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.