公开(公告)号：US09515093B2

公开(公告)日：2016-12-06

申请号：US14466317

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L29/12 ,  H01L29/10 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/124 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/443 ,  H01L21/76852 ,  H01L23/53238 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

Abstract translation: 如下提供薄膜晶体管阵列面板。 栅电极设置在基板上。 半导体层设置在栅电极上。 栅极绝缘层设置在栅电极和半导体层之间。 源电极设置在半导体层的第一侧上，具有第一侧表面。 漏电极设置在半导体层的第二侧上，具有第二侧表面。 第一和第二侧表面限定了与栅电极重叠的间隔。 金属硅化物层设置在第一和第二侧表面上。 在金属硅化物层，源电极和漏电极上设置钝化层。 钝化层不与第一和第二侧表面接触。

公开(公告)号：US20150044817A1

公开(公告)日：2015-02-12

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Wood Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/66 ,  H01L21/477 ,  H01L21/441 ,  H01L21/02 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US11133370B2

公开(公告)日：2021-09-28

申请号：US16742449

申请日：2020-01-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kap Soo Yoon ,  Chan Woo Yang ,  June Whan Choi

IPC: H01L27/14 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  H01L51/00

Abstract: An organic light emitting diode display includes a substrate including a display area and a pad area, a first thin film transistor disposed on the display area, an organic light emitting diode connected to the first thin film transistor, a pad electrode disposed on the pad area and a pad contact electrode disposed on an upper portion of the pad electrode and electrically connected to the pad electrode. The organic light emitting diode includes an anode, an organic emission layer, and a cathode. The anode includes a lower layer, an intermediate layer, and an upper layer. The pad contact electrode is formed of a material of the lower layer of the anode.

公开(公告)号：US09082795B2

公开(公告)日：2015-07-14

申请号：US14477587

申请日：2014-09-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Chan Woo Yang ,  Seung-Ho Jung ,  Doo Na Kim ,  Bo Sung Kim ,  Eun Hye Park ,  June Whan Choi

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01B1/06 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio ( R , R ⁡ [ mol ⁢ ⁢ % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），摩尔比（R，R⁡[mol⁢％] = [In] [In + Zn + Sn]×100） 对于半导体层中的金属，铟（In）的含量小于约20％，更具体地说，摩尔比（R，R⁡[mol·⁢％] = [In] [In + Zn + Sn]×100 ）的半导体层中的金属的In（In）为约5％至约13％。

公开(公告)号：US12113058B2

公开(公告)日：2024-10-08

申请号：US17215682

申请日：2021-03-29

Applicant: Samsung Display Co., LTD.

Inventor： Kang Moon Jo ,  An Su Lee ,  June Whan Choi

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0292 ,  H01L27/0288 ,  H01L27/0296

Abstract: A display device includes a substrate including a display area and a non-display area; a semiconductor layer including a source area, a channel area, and a drain area and disposed in the non-display area of the substrate; a gate electrode overlapping the channel area of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the channel area of the semiconductor layer; a source electrode electrically connected to the source area of the semiconductor layer; and a drain electrode electrically connected to the drain area of the semiconductor layer, wherein a lateral side of the gate electrode overlaps the drain electrode.

公开(公告)号：US11825712B2

公开(公告)日：2023-11-21

申请号：US17446036

申请日：2021-08-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kap Soo Yoon ,  Chan Woo Yang ,  June Whan Choi

IPC: H01L21/00 ,  H10K59/131 ,  H10K50/818 ,  H10K50/844 ,  H10K59/38 ,  H10K59/123 ,  H10K59/126 ,  H10K71/00 ,  H10K59/12 ,  H10K102/00 ,  H10K102/10

CPC classification number: H10K59/131 ,  H10K50/818 ,  H10K50/844 ,  H10K59/123 ,  H10K59/126 ,  H10K59/38 ,  H10K71/00 ,  H10K59/1201 ,  H10K71/621 ,  H10K2102/00 ,  H10K2102/103 ,  H10K2102/351

Abstract: An organic light emitting diode display includes a substrate including a display area and a pad area, a first thin film transistor disposed on the display area, an organic light emitting diode connected to the first thin film transistor, a pad electrode disposed on the pad area and a pad contact electrode disposed on an upper portion of the pad electrode and electrically connected to the pad electrode. The organic light emitting diode includes an anode, an organic emission layer, and a cathode. The anode includes a lower layer, an intermediate layer, and an upper layer. The pad contact electrode is formed of a material of the lower layer of the anode.

公开(公告)号：US11943976B2

公开(公告)日：2024-03-26

申请号：US16892988

申请日：2020-06-04

Applicant: Samsung Display Co., LTD.

Inventor： Seung Sok Son ,  Woo Geun Lee ,  Seul Ki Kim ,  Kap Soo Yoon ,  Hyun Woong Baek ,  Jae Hyun Lee ,  Su Jung Jung ,  Jung Kyoung Cho ,  Seung Ha Choi ,  June Whan Choi

IPC: G02F1/1362 ,  G09G3/32 ,  H10K59/121 ,  H10K59/131 ,  H10K59/38 ,  H10K59/12

CPC classification number: H10K59/131 ,  G09G3/32 ,  G09G2300/0426 ,  G09G2310/0202 ,  H10K59/1201

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.

公开(公告)号：US09406785B2

公开(公告)日：2016-08-02

申请号：US14521043

申请日：2014-10-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/441 ,  H01L21/02 ,  H01L21/385 ,  H01L29/66 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US08895977B2

公开(公告)日：2014-11-25

申请号：US13673195

申请日：2012-11-09

Applicant: Samsung Display Co., Ltd.

Inventor： Doo Hyoung Lee ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L21/786 ,  H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.

Abstract translation: 薄膜晶体管包括衬底，设置在衬底上的氧化物半导体层，与氧化物半导体层重叠的栅电极，设置在氧化物半导体层和栅电极之间的栅极绝缘层，以及源极 电极和与氧化物半导体层至少部分重叠并且彼此间隔开的漏电极。 栅极绝缘层包括包含第一材料的氧化物。 氧化物半导体层包括与第一材料相同的材料和第二材料的氧化物，源电极和漏极包括包含与第二材料相同的材料的氧化物和第三材料，以及晶界 不形成在栅极绝缘层和氧化物半导体层中的至少一个之间或氧化物半导体层以及源电极和漏电极之间的界面上。

公开(公告)号：US20130320327A1

公开(公告)日：2013-12-05

申请号：US13673195

申请日：2012-11-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung LEE ,  Bo Sung Kim ,  Chan Woo Yang ,  Seung-Ho Jung ,  Yeon Taek Jeong ,  June Whan Choi ,  Tae-Young Choi

IPC: H01L29/786 ,  H01L21/385

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/385 ,  H01L21/441 ,  H01L21/477 ,  H01L29/7869

Abstract: A thin film transistor includes a substrate, an oxide semiconductor layer that is disposed on the substrate, a gate electrode that overlaps with the oxide semiconductor layer, a gate insulating layer that is disposed between the oxide semiconductor layer and the gate electrode, and a source electrode and a drain electrode that at least partially overlap with the oxide semiconductor layer and are spaced from each other. The gate insulating layer includes an oxide including a first material. The oxide semiconductor layer includes an oxide which includes a same material as the first material and a second material, and the source electrode and the drain electrode include an oxide that includes a same material as the second material and a third material, and a grain boundary is not formed on an interface between at least one of the gate insulating layer and the oxide semiconductor layer or between the oxide semiconductor layer, and the source electrode and the drain electrode.