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    Oxide semicondutor thin film transistor
    1.
    发明授权
    Oxide semicondutor thin film transistor 有权
    氧化物半导体薄膜晶体管

    公开(公告)号：US09093540B2

    公开(公告)日：2015-07-28

    申请号：US13683468

    申请日：2012-11-21

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/86

    CPC分类号： H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

    摘要： The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region include an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

    摘要翻译： 本发明涉及薄膜晶体管，薄膜晶体管阵列面板及其制造方法。 根据本发明的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 与所述栅电极重叠的沟道区，位于所述沟道区与所述栅电极之间的所述栅绝缘层; 以及源极区域和漏极区域，其相对于沟道区域彼此面对，位于与沟道区域相同的层中，并且连接到沟道区域，其中沟道区域，源极区域和漏极区域包括 氧化物半导体，其中源极区域和漏极区域的载流子浓度大于沟道区域的载流子浓度。

    THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF 审中-公开
    薄膜晶体管，薄膜晶体管阵列及其制造方法

    公开(公告)号：US20150333154A1

    公开(公告)日：2015-11-19

    申请号：US14808769

    申请日：2015-07-24

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun LEE ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L27/12 ,  H01L21/268 ,  H01L21/308 ,  H01L21/02 ,  H01L29/786 ,  H01L21/28

    CPC分类号： H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

    摘要： The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

    摘要翻译： 本发明涉及薄膜晶体管，薄膜晶体管阵列面板及其制造方法。 根据本发明的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 与所述栅电极重叠的沟道区，位于所述沟道区与所述栅电极之间的所述栅绝缘层; 以及源极区域和漏极区域，其相对于沟道区域彼此面对，位于与沟道区域相同的层中，并且连接到沟道区域，其中沟道区域，源极区域和漏极区域包括 氧化物半导体，其中源极区域和漏极区域的载流子浓度大于沟道区域的载流子浓度。

    Thin film transistor array panel
    3.
    再颁专利
    Thin film transistor array panel 有权

    公开(公告)号：USRE48290E1

    公开(公告)日：2020-10-27

    申请号：US16130107

    申请日：2018-09-13

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/268 ,  H01L29/423 ,  H01L27/12 ,  H01L21/28 ,  H01L29/40 ,  H01L21/02 ,  H01L29/86

    摘要： A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.

    Thin film transistor array panel
    6.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号：US09455333B2

    公开(公告)日：2016-09-27

    申请号：US14809830

    申请日：2015-07-27

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/40 ,  H01L21/28 ,  H01L21/268 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  H01L29/86

    CPC分类号： H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

    摘要： A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.

    摘要翻译： 薄膜晶体管阵列面板包括衬底，设置在衬底上的遮光膜，覆盖遮光膜的缓冲层和设置在缓冲层上的沟道区。 源极区域和漏极区域设置在与沟道区域相同的层中。 栅极绝缘层设置在沟道区上，并且栅电极与沟道区重叠，栅极绝缘层介于栅电极和沟道区之间。 钝化层设置在栅电极，源极区，漏极区和缓冲层上。 源电极和漏极设置在钝化层上，其中沟道区，源区和漏区包括氧化物半导体，并且其中源极区和漏极区的载流子浓度大于 渠道区域。