公开(公告)号：US11903254B2

公开(公告)日：2024-02-13

申请号：US17739010

申请日：2022-05-06

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Eun Choi ,  Deok Hoi Kim ,  Jeong Hwan Kim ,  Jong Baek Seon ,  Jun Cheol Shin ,  Jae Hak Lee

IPC: H10K59/12 ,  H10K59/121 ,  H10K59/123 ,  H10K59/126 ,  H10K77/10 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66 ,  H10K102/00

CPC classification number: H10K59/1213 ,  H10K59/123 ,  H10K59/126 ,  H10K59/1216 ,  H10K77/111 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/78675 ,  H10K59/1201 ,  H10K2102/311

Abstract: A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer.

公开(公告)号：US09991287B2

公开(公告)日：2018-06-05

申请号：US15478386

申请日：2017-04-04

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Hun Lim ,  Jong Baek Seon ,  Kyoung Seok Son ,  Eok Su Kim ,  Tae Sang Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer to not overlap the gate electrode, wherein a first edge of the gate electrode is aligned with a second edge of the semiconductor layer in a direction that is perpendicular to the substrate.

公开(公告)号：US11937457B2

公开(公告)日：2024-03-19

申请号：US17410699

申请日：2021-08-24

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Baek Seon ,  Deok Hoi Kim ,  Hun Kim

IPC: H10K59/121 ,  H01L27/12 ,  H10K77/10 ,  H10K102/00

CPC classification number: H10K59/1213 ,  H01L27/1218 ,  H10K77/111 ,  H10K2102/311

Abstract: A display device is provided. The display device comprises a first base substrate, a first barrier layer disposed on the first base substrate, a second base substrate disposed on the first barrier layer, a first sub-substrate disposed on the second base substrate and comprising at least one dopant selected from a group consisting of: fluorine (F), boron (B), arsenic (As), phosphorus (P), chlorine (Cl), bromine (Br), iodine (I), astatine (At), sulfur (S), selenium (Se), argon (Ar), and tellurium (Te), a second barrier layer disposed on the first sub-substrate, a second buffer layer disposed on the second barrier layer, a first buffer layer disposed on the second buffer layer, at least one transistor disposed on the first buffer layer, and an organic light-emitting diode disposed on the at least one transistor.

公开(公告)号：US11342401B2

公开(公告)日：2022-05-24

申请号：US16839796

申请日：2020-04-03

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Eun Choi ,  Deok Hoi Kim ,  Jeong Hwan Kim ,  Jong Baek Seon ,  Jun Cheol Shin ,  Jae Hak Lee

IPC: H01L27/32 ,  H01L51/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: A display device includes: a base substrate having a display region including a first region and a second region, and a non-display region; a first semiconductor layer including polysilicon at the second region; a first conductive layer on a first insulating layer, and including a bottom gate electrode at the first region and a second-first gate electrode at the second region; a second semiconductor layer including an oxide on a second insulating layer at the first region; a second conductive layer on a third insulating layer, and including a top gate electrode at the first region and a second-second gate electrode at the second region; and a third conductive layer on a fourth insulating layer, and including a first source electrode and a first drain electrode connected to the second semiconductor layer, and a second source electrode and a second drain electrode connected to the first semiconductor layer.