公开(公告)号：US09660186B2

公开(公告)日：2017-05-23

申请号：US15175463

申请日：2016-06-07

Applicant: Samsung ELectronics Co., Ltd.

Inventor： Jinhye Bae ,  Wonjun Lee ,  Yoonsung Han ,  Hoon Han ,  Kyu-Man Hwang ,  Yongsun Ko

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L21/66

CPC classification number: H01L43/12 ,  H01L22/12 ,  H01L27/101 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.

公开(公告)号：US11462584B2

公开(公告)日：2022-10-04

申请号：US17018539

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonsung Han ,  Seung Pil Ko

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L23/532 ,  G11C11/16 ,  H01L43/12

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

公开(公告)号：US10804320B2

公开(公告)日：2020-10-13

申请号：US15791503

申请日：2017-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonsung Han ,  Seung Pil Ko

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L23/532 ,  G11C11/16 ,  H01L43/12

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.