公开(公告)号：US11127472B2

公开(公告)日：2021-09-21

申请号：US16806535

申请日：2020-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Jun Lee ,  Seung Bum Kim ,  Il Han Park

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C11/56 ,  G11C29/50 ,  G11C29/42 ,  G11C29/00 ,  G06F11/07 ,  G11C16/04

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

公开(公告)号：US10607705B2

公开(公告)日：2020-03-31

申请号：US16047384

申请日：2018-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Jun Lee ,  Seung Bum Kim ,  Il Han Park

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C11/56 ,  G11C29/50 ,  G11C29/42 ,  G11C29/00 ,  G06F11/07 ,  G11C16/04

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

公开(公告)号：US11107537B2

公开(公告)日：2021-08-31

申请号：US16987658

申请日：2020-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  H01L27/115 ,  G11C16/08

Abstract: A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

公开(公告)号：US11955183B2

公开(公告)日：2024-04-09

申请号：US17827852

申请日：2022-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

IPC: G11C16/24 ,  G11C16/12 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/12 ,  G11C16/26

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

公开(公告)号：US11682463B2

公开(公告)日：2023-06-20

申请号：US17407369

申请日：2021-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Jun Lee ,  Seung Bum Kim ,  Il Han Park

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C11/56 ,  G11C29/50 ,  G11C29/42 ,  G11C29/00 ,  G06F11/07 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/07 ,  G11C11/5642 ,  G11C16/30 ,  G11C16/349 ,  G11C16/3427 ,  G11C29/00 ,  G11C29/42 ,  G11C29/50 ,  G11C29/50004 ,  G11C16/0483 ,  G11C2029/5002

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

公开(公告)号：US20190214091A1

公开(公告)日：2019-07-11

申请号：US16047384

申请日：2018-07-27

Applicant: Samsung Electronics Co., LTD.

Inventor： Han Jun Lee ,  Seung Bum Kim ,  Il Han Park

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C11/56

Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

公开(公告)号：US11380404B2

公开(公告)日：2022-07-05

申请号：US17099678

申请日：2020-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

IPC: G11C16/24 ,  G11C16/12 ,  G11C16/26

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.