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公开(公告)号：US20230344250A1
公开(公告)日：2023-10-26
申请号：US18218168
申请日：2023-07-05
发明人： Kyunghwan LEE , Yeongil KIM
CPC分类号： H02J7/00308 , G06F1/266 , H02M3/158
摘要： According to certain embodiments, an electronic device comprises: a battery; an interface module; a detection module electrically connected with the interface module, the detection module configured to detect than an external electronic device for receiving power is connected to the interface module; a protection module electrically connected with the interface module and comprising a first switching element; and a charging module electrically connected with the protection module, the detection module, and the battery, and comprising a voltage conversion circuit and a second switching element, the charging module configured to provide a first power to the protection module when the detection module detects connection of the external electronic device, wherein the first switching element is configured to turn on after receiving the first power, wherein the charging module is configured to raise a power from the battery to a designated value through the voltage conversion circuit, thereby resulting in a second power, and, when a designated first time is elapsed after the power from the battery is raised to the designated value, turn on the second switching element, thereby providing the second power to the protection module.
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公开(公告)号：US20230247103A1
公开(公告)日：2023-08-03
申请号：US18300066
申请日：2023-04-13
发明人： Jungho PARK , Yul KIM , Sejeong KWON , Soohyung KIM , Wonsuk YANG , Kyunghwan LEE , Junhyuk LEE
CPC分类号： H04L67/535 , H04L43/04 , H04L41/16
摘要： An electronic apparatus is provided. The electronic apparatus includes a communication interface, a memory storing log data with respect to external devices connected to the electronic apparatus, and a processor configured to identify a plurality of external devices having a history of being connected to the same internet protocol (IP) based on the log data, acquire, based on the log data, a first feature vector with respect to a relationship between the plurality of external devices and a second feature vector with respect to each of the plurality of external devices, acquire a graph of the relationship between the plurality of external devices based on the first feature vector and the second feature vector, and define at least one group configured by the plurality of external devices based on the graph.
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公开(公告)号：US20230112067A1
公开(公告)日：2023-04-13
申请号：US17880083
申请日：2022-08-03
发明人： Kyunghwan LEE , Youngdeog KOH , Kwangjoo KIM , Jinju KIM , Jihwan CHUN
摘要： A decoration panel for home appliances having excellent reflectivity and durability, the decoration panel being applicable to outer sides of various home appliances, a home appliance including the decoration panel, and a method for manufacturing the decoration panel. More specifically, the decoration panel for home appliances includes: an aluminum substrate with one surface in which an engraved pattern having a preset width and a preset depth is formed, the engraved pattern having micro unevenness formed in a surface of the engraved pattern; a porous aluminum oxide layer formed on the engraved pattern; and a sealing layer formed to close a plurality of pores of the porous aluminum oxide layer, wherein an edge of the aluminum substrate is in a Chamfering (C) shape or a Rounding (R) shape.
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公开(公告)号：US20230049653A1
公开(公告)日：2023-02-16
申请号：US17722672
申请日：2022-04-18
发明人： Kyunghwan LEE , Yongseok KIM , Dongsoo WOO , Junhee LIM
IPC分类号： H01L23/535 , H01L25/065 , H01L25/18 , H01L23/00 , H01L27/11556 , H01L27/11582
摘要： A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.
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公开(公告)号：US20220029095A1
公开(公告)日：2022-01-27
申请号：US17192093
申请日：2021-03-04
发明人： Hyuncheol KIM , Yongseok KIM , Hyeoungwon SEO , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
摘要： A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.
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公开(公告)号：US20240170072A1
公开(公告)日：2024-05-23
申请号：US18510074
申请日：2023-11-15
发明人： Suhwan LIM , Kyunghwan LEE , Yongseok KIM
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/32
摘要： A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.
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公开(公告)号：US20230420993A1
公开(公告)日：2023-12-28
申请号：US18343511
申请日：2023-06-28
发明人： Kyunghwan LEE , Jungik HA , Geonhong MIN , Junhyeong LEE
CPC分类号： H02J50/12 , H02J2207/20 , H02J7/0047 , H02J7/00712
摘要： According to an embodiment, an electronic device for wirelessly receiving power may include: a power reception circuit including a coil, an impedance compensation circuit electrically connected to the power reception circuit, a rectifier circuit electrically connected to the impedance compensation circuit, a battery electrically connected to the rectifier circuit, and a control circuit electrically and/or operatively connected to the impedance compensation circuit, the rectifier circuit, and the battery. According to an embodiment, the control circuit may be configured to: rectify, by controlling the rectifier circuit, power received wirelessly from an external electronic device through the power reception circuit and the impedance compensation circuit into direct current (DC) power. According to an embodiment, the control circuit may be configured to identify at least one of a voltage or a current of the rectified DC power. According to an embodiment, the control circuit may be configured to determine a duty cycle of a control signal to control the impedance compensation circuit, based on the at least one of the voltage or the current. According to an embodiment, the control circuit may be configured to adjust a first voltage output by the impedance compensation circuit by controlling the impedance compensation circuit based on the duty cycle. According to an embodiment, impedance of the power reception circuit may be compensated based on the adjusted first voltage of the impedance compensation circuit.
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公开(公告)号：US20230309314A1
公开(公告)日：2023-09-28
申请号：US18108374
申请日：2023-02-10
发明人： Kyunghwan LEE , Yongseok Kim , Daewon Ha
CPC分类号： H10B51/20 , H10B51/10 , H01L29/516 , H01L29/78391
摘要： A three-dimensional ferroelectric random access memory (3D FeRAM) device includes: a gate electrode extending in a vertical direction on a substrate; a ferroelectric pattern and a gate insulation pattern stacked on the gate electrode in a horizontal direction to surround the gate electrode; first and second channels spaced apart from each other in the horizontal direction on an outer sidewall of the gate insulation pattern; first source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the first channel; and second source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the second channel.
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公开(公告)号：US20220199793A1
公开(公告)日：2022-06-23
申请号：US17443553
申请日：2021-07-27
发明人： Hyuncheol KIM , Yongseok KIM , Ilgweon KIM , Seokhan PARK , Kyunghwan LEE , Jaeho HONG
IPC分类号： H01L29/423 , H01L29/66 , H01L29/78 , H01L23/482
摘要： A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities
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公开(公告)号：US20220102352A1
公开(公告)日：2022-03-31
申请号：US17241860
申请日：2021-04-27
发明人： Kiseok LEE , Kyunghwan LEE , Dongoh KIM , Yongseok KIM , Hui-jung KIM , Min Hee CHO
IPC分类号： H01L27/108
摘要： A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
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