公开(公告)号：US20170092767A1

公开(公告)日：2017-03-30

申请号：US15379190

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok PARK ,  Jungho YOO ,  Jinyeong JOE ,  Bonyoung KOO ,  Dongsuk SHIN ,  Hongsik YOON ,  Byeongchan LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

公开(公告)号：US20160056269A1

公开(公告)日：2016-02-25

申请号：US14749037

申请日：2015-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jung LEE ,  Bonyoung KOO ,  Sunjung KIM ,  Jongryeol YOO ,  Seung Hun LEE ,  Poren TANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。

公开(公告)号：US20150214370A1

公开(公告)日：2015-07-30

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Bonyoung KOO ,  Seokhoon KIM ,  Chul KIM ,  Kwan Heum LEE ,  Byeongchan LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

Abstract translation: 半导体器件包括具有活性图案的衬底; 栅极结构，设置在所述有源图案上以穿过所述有源图案; 以及设置在栅极结构的两侧的源极/漏极区域。 有源图案包括栅极结构下方的第一区域和栅极结构两侧的第二区域。 每个第二区域的顶表面低于第一区域的顶表面。 源极/漏极区域分别设置在第二区域上，并且每个源极/漏极区域部分地覆盖每个第二区域的两个侧壁。