公开(公告)号：US20170373062A1

公开(公告)日：2017-12-28

申请号：US15494769

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Seung Yang ,  Dong Chan SUH ,  Chul KIM ,  Woo Bin SONG ,  Ji Eon YOON ,  Seung Ryul LEE

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: The semiconductor device includes a first multi-channel active pattern protruding from a substrate, and having a first height, a second multi-channel active pattern on the substrate, being spaced apart from the substrate, and having a second height that is less than the first height, and a gate electrode on the substrate, intersecting the first multi-channel active pattern and the second multi-channel active pattern.

公开(公告)号：US20150214370A1

公开(公告)日：2015-07-30

申请号：US14491117

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Bonyoung KOO ,  Seokhoon KIM ,  Chul KIM ,  Kwan Heum LEE ,  Byeongchan LEE ,  Sujin JUNG

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.

Abstract translation: 半导体器件包括具有活性图案的衬底; 栅极结构，设置在所述有源图案上以穿过所述有源图案; 以及设置在栅极结构的两侧的源极/漏极区域。 有源图案包括栅极结构下方的第一区域和栅极结构两侧的第二区域。 每个第二区域的顶表面低于第一区域的顶表面。 源极/漏极区域分别设置在第二区域上，并且每个源极/漏极区域部分地覆盖每个第二区域的两个侧壁。

公开(公告)号：US20150162332A1

公开(公告)日：2015-06-11

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Bon-Young KOO ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

公开(公告)号：US20170186609A1

公开(公告)日：2017-06-29

申请号：US15363139

申请日：2016-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Eon YOON ,  Chul KIM ,  Sang Moon LEE ,  Seung Ryul LEE

IPC: H01L21/02 ,  H01L29/32

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02598 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01L29/32

Abstract: A semiconductor single crystal structure may include a substrate; a defect trapping stack disposed on the substrate; and a semiconductor single crystal disposed on the defect trapping stack, and having a lattice mismatch with a crystal of the substrate, in which the defect trapping stack may include a first dielectric layer disposed on the substrate, and having at least one first opening, a second dielectric layer disposed on the first dielectric layer, and having at least one second opening, a third dielectric layer disposed on the second dielectric layer, and having at least one third opening, and a fourth dielectric layer disposed on the third dielectric layer, and having at least one fourth opening, and in which the semiconductor single crystal may extend to a region of the substrate defined in the at least one first opening through the at least one first to fourth opening.