-
公开(公告)号:US20190198639A1
公开(公告)日:2019-06-27
申请号:US16037922
申请日:2018-07-17
Inventor: Jin Bum KIM , MunHyeon KIM , Hyoung Sub KIM , Tae Jin PARK , Kwan Heum LEE , Chang Woo NOH , Maria TOLEDANO LU QUE , Hong Bae PARK , Si Hyung LEE , Sung Man WHANG
IPC: H01L29/66 , H01L29/78 , H01L29/423 , H01L29/786
CPC classification number: H01L29/66545 , H01L29/42392 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/78696
Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
-
公开(公告)号:US20220020849A1
公开(公告)日:2022-01-20
申请号:US17176667
申请日:2021-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong Hyuk YEOM , Kwan Heum LEE , Jun Kyum KIM , Seong Hwa PARK , So Hyun SEO
IPC: H01L29/06 , H01L29/786 , H01L29/423 , H01L27/092 , H01L29/10 , H01L29/08 , H01L21/8238
Abstract: A semiconductor device includes a gate electrode extending in a first direction, on a substrate, first outer spacers extending along side surfaces of the gate electrode, a first active pattern extending in a second direction, which intersects the first direction, to penetrate the gate electrode and the first outer spacers, epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers, second outer spacers between the first outer spacers and the epitaxial patterns and inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns, wherein in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers.
-
3.
公开(公告)号:US20150214370A1
公开(公告)日:2015-07-30
申请号:US14491117
申请日:2014-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinbum KIM , Bonyoung KOO , Seokhoon KIM , Chul KIM , Kwan Heum LEE , Byeongchan LEE , Sujin JUNG
CPC classification number: H01L29/0847 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.
Abstract translation: 半导体器件包括具有活性图案的衬底; 栅极结构,设置在所述有源图案上以穿过所述有源图案; 以及设置在栅极结构的两侧的源极/漏极区域。 有源图案包括栅极结构下方的第一区域和栅极结构两侧的第二区域。 每个第二区域的顶表面低于第一区域的顶表面。 源极/漏极区域分别设置在第二区域上,并且每个源极/漏极区域部分地覆盖每个第二区域的两个侧壁。
-
4.
公开(公告)号:US20210013324A1
公开(公告)日:2021-01-14
申请号:US17038004
申请日:2020-09-30
Inventor: Jin Bum KIM , MunHyeon KIM , Hyoung Sub KIM , Tae Jin PARK , Kwan Heum LEE , Chang Woo NOH , Maria TOLEDANO LU QUE , Hong Bae PARK , Si Hyung LEE , Sung Man WHANG
IPC: H01L29/66 , H01L29/78 , H01L29/423 , H01L29/786
Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.
-
公开(公告)号:US20170352759A1
公开(公告)日:2017-12-07
申请号:US15685459
申请日:2017-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Nam Kyu KIM , Dong Chan SUH , Kwan Heum LEE , Byeong Chan LEE , Cho Eun LEE , Su Jin JUNG , Gyeom KIM , Ji Eon YOON
IPC: H01L29/78 , H01L29/165 , H01L29/417 , H01L29/08
CPC classification number: H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/7834
Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
-
6.
公开(公告)号:US20170133275A1
公开(公告)日:2017-05-11
申请号:US15413472
申请日:2017-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoon Hae KIM , Jin Wook LEE , Jong Ki JUNG , Myung II KANG , Kwang Yong YANG , Kwan Heum LEE , Byeong Chan LEE
IPC: H01L21/8234 , H01L21/308 , H01L29/08 , H01L21/311 , H01L27/092 , H01L29/78 , H01L27/088 , H01L29/165 , H01L27/11 , H01L21/8238 , H01L29/66 , H01L21/3105
CPC classification number: H01L21/823431 , H01L21/308 , H01L21/31053 , H01L21/31111 , H01L21/31116 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/1104 , H01L29/0847 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7848
Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
-
-
-
-
-