公开(公告)号：US20190244965A1

公开(公告)日：2019-08-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1108 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US10186579B2

公开(公告)日：2019-01-22

申请号：US15862308

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok Min ,  Sung Dae Suk ,  JeongYun Lee

IPC: H01L23/52 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern. The source/drain regions fill the pair of recesses in the first active pattern. Each of the source/drain regions include a first semiconductor pattern in the recess and a second semiconductor pattern on the first semiconductor pattern. The source/drain region have an upper portion whose width is less than a width of its lower portion. The second semiconductor pattern has an upper portion whose width is less than a width of its lower portion. The upper portion of the second semiconductor pattern is positioned higher than a top surface of the channel region.

公开(公告)号：US10332898B2

公开(公告)日：2019-06-25

申请号：US15635583

申请日：2017-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US20180190772A1

公开(公告)日：2018-07-05

申请号：US15862308

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Sung Dae Suk ,  JeongYun Lee

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: A semiconductor device includes a device isolation layer on a substrate, a first active pattern defined by the device isolation layer, and source/drain regions. The first active pattern extends in a first direction and includes a channel region between a pair of recesses formed at an upper portion of the first active pattern. The source/drain regions fill the pair of recesses in the first active pattern. Each of the source/drain regions include a first semiconductor pattern in the recess and a second semiconductor pattern on the first semiconductor pattern. The source/drain region have an upper portion whose width is less than a width of its lower portion. The second semiconductor pattern has an upper portion whose width is less than a width of its lower portion. The upper portion of the second semiconductor pattern is positioned higher than a top surface of the channel region.

公开(公告)号：US10861860B2

公开(公告)日：2020-12-08

申请号：US16386407

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungsoo Hong ,  JeongYun Lee ,  GeumJung Seong ,  HyunHo Jung ,  Minchan Gwak ,  Kyungseok Min ,  Youngmook Oh ,  Jae-Hoon Woo ,  Bora Lim

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

公开(公告)号：US10461195B2

公开(公告)日：2019-10-29

申请号：US15864330

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taesoon Duyeon Kwon ,  JeongYun Lee ,  A-reum Ji ,  Kyungseok Min ,  GeumJung Seong

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/165

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

公开(公告)号：US10026809B1

公开(公告)日：2018-07-17

申请号：US15662248

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung Seong ,  JeongYun Lee ,  SeungSoo Hong ,  KyungSeok Min ,  SeungJu Park ,  Youngmook Oh ,  Bora Lim

IPC: H01L29/76 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/764 ,  H01L27/088 ,  H01L29/08 ,  H01L23/535

Abstract: Active patterns protrude from a substrate. The active patterns include a first active pattern, a second active pattern spaced apart from the first active pattern at a first distance, and a third active pattern spaced apart from the second active pattern at a second distance greater than the first distance. A gate spacer is disposed on sidewalls of a gate electrode running across the active patterns. Source/drain regions include a first to a third source/drain regions disposed on a region of one of the active patterns. The region of one of the active patterns is disposed adjacent to a side of the gate electrode. First and second protective insulation patterns are disposed on the substrate between the first and second active patterns below the first and second source/drain regions and between the second and third active patterns below the second and third source/drain regions, respectively.