公开(公告)号：US10824580B2

公开(公告)日：2020-11-03

申请号：US15815048

申请日：2017-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ho Kim ,  Kwang Soo Park ,  Ji Woon Park

IPC: G06F12/00 ,  G06F13/40 ,  G11C5/02 ,  G11C8/12 ,  G11C7/22 ,  G11C5/06 ,  G06F13/42 ,  G11C5/04 ,  G11C11/4063 ,  G11C7/10 ,  G06F13/16 ,  G11C29/02

Abstract: A semiconductor device includes a plurality of memory chips arranged in a line on a substrate, and a bus connected to the plurality of memory chips and configured to sequentially supply an electrical signal to the plurality of memory chips in accordance with a fly-by topology. An order in which the electrical signal is supplied to the plurality of memory chips is different from an order in which the plurality of memory chips is arranged in the line on the substrate.

公开(公告)号：US10389951B2

公开(公告)日：2019-08-20

申请号：US15721435

申请日：2017-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyoung Park ,  Byung Ho Kim ,  Jae Joon Moon ,  Jeong Won Lee ,  Han Sung Kim ,  Woo Seok Choi ,  Shuichi Shimokawa ,  Takafumi Usui

IPC: H04N5/235 ,  H04N5/355 ,  H04N5/232 ,  H04N9/69

Abstract: An electronic device includes a lens part that receives light from a subject, an image sensor that receives the light of the lens part from a group of pixels arranged two-dimensionally, and an processor that processes an image signal of the image sensor. The image sensor performs a read-out operation at a speed to prevent blurring of an image. The processor temporarily stores image data by the read-out operation in a memory, loads a plurality of images stored in the memory to generate an image, of which the number of bits is expanded compared with the image signal of the image sensor, and performs gamma processing on the image, of which the number of bits is expanded, to generate an image compressed to the same number of bits as the image signal of the image sensor.

公开(公告)号：US10770416B2

公开(公告)日：2020-09-08

申请号：US16282980

申请日：2019-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ho Kim ,  Jae Hoon Choi ,  Joo Young Choi

IPC: H01L23/00

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including at least one insulating layer and redistribution layer, the redistribution layer including a via penetrating through the insulating layer and a RDL pattern connected to the via while being located on an upper surface of the insulating layer; a semiconductor chip disposed on the first surface and including a connection pad connected to the redistribution layer; and an encapsulant disposed on the first surface and encapsulating the semiconductor chip. The redistribution layer includes a seed layer disposed on a surface of the insulating layer and a plating layer disposed on the seed layer. An interface between the insulating layer and a portion of the seed layer constituting the via includes a first uneven surface with a surface roughness of 30 nm or more.

公开(公告)号：US20250062240A1

公开(公告)日：2025-02-20

申请号：US18611488

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MyungDo Cho ,  Youngchan Ko ,  Byung Ho Kim ,  Yongkoon Lee ,  Jeongho Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: An example semiconductor package includes a first redistribution layer, a bridge chip attached to a top surface of the first redistribution layer, a mold layer on the first redistribution layer and enclosing the bridge chip, a second redistribution layer disposed on the mold layer, a conductive post extending through the mold layer vertically and connecting the first redistribution layer and the second redistribution layer, and a first semiconductor chip mounted on the second redistribution layer. The first redistribution layer includes a pad layer and an interconnection layer disposed on the pad layer. The pad layer includes a first insulating layer and pads in the first insulating layer. Top surfaces of the pads are exposed to an outside of a top surface of the first insulating layer, and bottom surfaces of the pads are exposed to an outside of a bottom surface of the first insulating layer.

公开(公告)号：US11476215B2

公开(公告)日：2022-10-18

申请号：US17243889

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Choi ,  Doo Hwan Lee ,  Joo Young Choi ,  Sung Han ,  Byung Ho Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13 ,  H01L23/538

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

公开(公告)号：US10402620B2

公开(公告)日：2019-09-03

申请号：US15981311

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ho Kim ,  Da Hee Kim ,  Joon Sung Kim ,  Joo Young Choi ,  Hee Sook Park ,  Tae Wook Kim

IPC: G06K9/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/053 ,  H01L23/055 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

公开(公告)号：US20210265296A1

公开(公告)日：2021-08-26

申请号：US17243889

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Choi ,  Doo Hwan Lee ,  Joo Young Choi ,  Sung Han ,  Byung Ho Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13

Abstract: A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

公开(公告)号：US11011485B2

公开(公告)日：2021-05-18

申请号：US16294083

申请日：2019-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Choi ,  Doo Hwan Lee ,  Joo Young Choi ,  Sung Han ,  Byung Ho Kim

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

公开(公告)号：US20200091099A1

公开(公告)日：2020-03-19

申请号：US16294083

申请日：2019-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Choi ,  Doo Hwan Lee ,  Joo Young Choi ,  Sung Han ,  Byung Ho Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13

Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

公开(公告)号：US10515916B2

公开(公告)日：2019-12-24

申请号：US16025267

申请日：2018-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Jung Byun ,  Byung Ho Kim ,  Pyung Hwa Han ,  Joo Young Choi ,  Ung Hui Shin

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/28 ,  H01L23/522

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip. The first interconnection member includes a first insulating layer in contact with the second interconnection member, a first redistribution layer disposed on a surface of the first insulating layer in contact with the second interconnection member and electrically connected to the connection pads, and a blocking layer disposed on the surface of the first insulating layer on which the first redistribution layer is disposed and surrounding the through-hole.